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參數(shù)資料
| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 31/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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2
–
15
2.2.9
Phy Access Register at 24h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
R
PHYRGAD
PHYRGDATA
PHYRXAD
PHYRXDATA
W
The Phy access register allows access to the registers in the attached Phy. The most significant 16 bits send
read and write requests to the Phy registers. The least significant 16 bits are for the Phy to respond to a read
request sent by the TSB12LV32. The Phy access register also allows the Phy interface to send information
back to the TSB12LV32. When the Phy interface sends new information to the TSB12LV32, the Phy
register-information-receive (PhyRRx) interrupt is set. The Phy acess register is at address 24h and is a
read/write register. The power-up reset value of this register =
0000_0000
’
h
.
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
RDPHY
Read Phy
register
R/W
When RDPHY is set, the TSB12LV32 sends a read register
request with the address equal to the PHYRGAD field to the Phy
interface. This bit is cleared when the request is sent.
1
WRPHY
Write Phy
register
R/W
When WRPHY is set, the TSB12LV32 sends a write register
request with the address equal to the PHYRGAD field to the Phy
interface. This bit is cleared when the request is sent.
2
–
3
RESERVED
RESERVED
4
–
7
PHYRGAD
Phy-register
address
R/W
PHYRGAD is the address of the Phy register that is to be
accessed.
8
–
15
PHYRGDATA
Phy-register
data
R/W
PHYRGDATA is the data to be written to the Phy register
indicated in PHYRGAD.
16
–
19
RESERVED
RESERVED
20
–
23
PHYRXAD
Phy-register
received ad-
dress
R/W
PHYRXAD is the address of the register from which
PHYRXDATA came. For testing, these bits can be set only when
the REGRW bit has been set in the diagnostics register at20h.
24
–
31
PHYRXDATA
Phy-register
received
data
R/W
PHYRXDATA contains the data from the register addressed by
PHYRXAD. For testing, these bits can be set only when the
REGRW bit has been set in the diagnostics register at20h.
2.2.10
These registers are reserved for future use.
Reserved Registers at 28h
–
2Ch
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| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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