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參數(shù)資料
| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 29/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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2
–
13
2.2.7
Maint_Control Register at 1Ch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
PING VALUE
ACK
E
E
N
F
N
This register is used to generate test conditions. The control bits in this register allow errors to be inserted
into various places in the packets generated by this node. After the completion of error insertion, enabled
error-insertion controls are disabled. The power-up reset value of this register =
0000_0000
’
h
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
E_HCRC
Header CRC
Error
R/W
If E_HCRC is set, the packet header CRC component of the
next primary packet generated by this node shall be in error or
shall be invalid; otherwise, this bit has no effect. After the next
packet for this node is generated, this bit will be cleared.
1
E_DCRC
Data CRC
Error
R/W
If E_DCRC is set, the packet data CRC component of the next
primary packet generated by this node shall be in error or shall
be invalid; otherwise, this bit has no effect. After the next packet
for this node is generated, this bit will be cleared to zero im-
mediately upon transmission of the erroneous CRC.
2
NO_PKT
No Packet
R/W
If NO_PKT is set, the next primary packet to be generated by
this node shall be discarded. This bit will be cleared to zero im-
mediately after the next packet for this node is discarded.
3
F_ACK
Ack Field
R/W
If F_ACK is set, the ack field shall be used within the next ac-
knowledge packet generated by this node. This bit will be
cleared to zero immediately after the next acknowledge packet
for this node is generated.
4
NO_ACK
R/W
If NO_ACK is set, the next acknowledge packet (that would
normally have been generated by this node) is not sent. This bit
will be immediately cleared to zero when the next acknowledge
packet for this node is discarded.
5
–
7
RESERVED
Reserved
8
–
15
ACK
R/W
The 8-bit ACK field contains the 8-bit acknowledge packet
(ack_code and ack_parity) to be supplied when the F_ACK bit
indicates a modified acknowledge packet is to be generated.
16
–
23
RESERVED
Reserved
24
–
31
PINGVALUE
Ping timer
value
R/W
Ping timer value. This value reflects the time it takes a node
to respond to a ping packet. The granularity of this timer is
40 ns.
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| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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