參數(shù)資料
型號: TSB12LV01BPZ
英文描述: FPGA (Field-Programmable Gate Array)
中文描述: 總線控制器
文件頁數(shù): 34/106頁
文件大?。?/td> 605K
代理商: TSB12LV01BPZ
2
18
2.2.13
Header0 register must contain the isochronous header or the first quadlet of an asynchronous header if in
header insert mode. If not in header insert mode or if in receive mode, this register will be updated with the
received header. This register is write protected such that it cannot be written to unless automatic header
insert mode is enabled and DM is in transmit mode(i.e.,DMHDR=0 and DMRX=0). The power-up reset value
of this register =
0000_0000
h
Header0 Register at 38h
ISOCHRONOUS HEADER FOR QUADLET 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
PACKET DATA LENGTH
TAG
CHANNEL NUMBER
Tcode
Sync Bits
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
15
PacketData-
Length
Packet data
length
R/W
Packet data length in bytes.
16
17
TAG
Tag field
R/W
The tag field provides a high-level label for the format
of the data carried by the isochronous packet.
18
23
ChannelNumber
Channel
number
R/W
Channel number field
24
27
Tcode
Transmission
code
R/W
Packet transaction code
28
31
Syncbits
Synchronization
code
R/W
An application-specific control field
ASYNCHRONOUS HEADER FOR QUADLET 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
Tlabel
Tcode
Priority
Speed
Rt
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
13
RESERVED
RESERVED
14
15
Speed
Speed
R/W
Speed at which the Phy is to transmit a packet:
00 => S100
01 => S200
10 => S400
16
21
Tlabel
Transaction label
R/W
Transaction label
22
23
Rt
Retry code
R/W
The retry code specifies whether this packet is a retry
attempt and the retry protocol to be followed by the
destination node.
24
27
Tcode
Transaction code
R/W
The transaction code specifies the packet format and the
type of transaction that is to be performed.
28
31
Priority
Priority field
R/W
Priority code (applies only to the backplane Phy)
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