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參數(shù)資料
| 型號(hào)： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 78/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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6
–
3
power up. Hardware will check to insure the second quadlet is indeed the complement (logical inverse) of
the first quadlet. If there are any errors associated with the self-ID process, a self-ID interrupt will be
generated and the self-ID check register at 38h will be updated to reflect the error(s). This option can be
turned off by setting the FULLSID bit in the control register at 08h to 0.
6.5
Each quadlet in the GRF is internally 33-bits wide. The most significant bit (extra bit) is used to indicate
whether it is a packet token or a regular received quadlet (received header CRC and data CRC are checked
and not stored in GRF). This bit is called the CD bit, which value is reflected in bit #16 of the FIFO status
register. If CD bit is 1, the next quadlet read from the GRF is a packet token. If the CD bit is 0, the next quadlet
read from the GRF is a regular received quadlet. A packet token is stored as the first quadlet for each
received confirmed packet. The definition for packet token is shown in Table 6-1. Bit 0 is most significant
bit and bit 32 is the least significant bit.
GRF Stored Data Format
Table 6
–
1. Packet Token Definition
BITS
NAME
DESCRIPTION
0
CD
CD bit is 1 for packet token. This bit should only be read from the FIFO status
Register at 30h
1
–
2
Reserved
Reserved
3
–
16
QUADLET_COUNT
Expected quadlet count after packet token for this received packet.
17
–
19
Reserved
Reserved
20
–
24
ackCode
If bit 20 is 0, bits[21:24] are used as the Ack code that was sent back to the
transmitting node. If bit 20 is 1, it is an error condition and an error Ack code is sent to
the transmitting node.
25
–
26
Reserved
Reserved
27
–
28
SPEED
The speed code for the received packet.
00
–
100 Mb/s
01
–
200 Mb/s
10
–
400 Mb/s
29
–
32
Reserved
Reserved
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| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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