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參數(shù)資料
| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 96/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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8
–
3
8.2
To request access to the bus, to read or write a Phy register, or to control arbitration acceleration, the
TSB12LV32 sends a serial bit stream on the LREQ terminal as shown in Figure 8
–
2.
TSB12LV32 Service Request
… …
LR0
LR1
LR2
LR(n
–
2)
LR3
LR(n
–
1)
NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.
Figure 8
–
2. LREQ Request Stream
The length of the stream will vary depending on the type of request as shown in Table 8
–
3.
Table 8
–
3. Request Stream Bit Length
REQUEST TYPE
NUMBER OF BITS
Bus Request
7 or 8
Read Register Request
9
Write Register Request
17
Acceleration Control Request
6
Regardless of the type of request, a start-bit of 1 is required at the beginning of the stream, and a stop-bit
of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the
type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request
bit stream. The LREQ terminal is normally low.
Encoding for the request type is shown in Table 8
–
4.
Table 8
–
4. Request Type Encoding
LR1
–
LR3
NAME
DESCRIPTION
000
ImmReq
Immediate bus request. Upon detection of idle, the Phy takes control of the bus immediately
without arbitration.
001
IsoReq
Isochronous bus request. Upon detection of idle, the Phy arbitrates for the bus without waiting
for a subaction gap.
010
PriReq
Priority bus request. The Phy arbitrates for the bus after a subaction gap, ignores the fair
protocol.
011
FairReq
Fair bus request. The Phy arbitrates for the bus after a subaction gap, follows the fair protocol.
100
RdReg
The Phy returns the specified register contents through a status transfer.
101
WrReg
Write to the specified register.
110
AccelCtl
Enable or disable asynchronous arbitration acceleration.
111
Reserved
Reserved.
For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 8
–
5.
Table 8
–
5. Bus Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer (always 1).
1
–
3
Request Type
Indicates the type of bus request (see Table 8
–
4).
4
–
6
Request Speed
Indicates the speed at which the Phy will send the data for this request (see Table 8
–
6)
for the encoding of this field.
7
Stop Bit
Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.
The 3-bit request speed field used in bus requests is shown in Table 8
–
6.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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