參數(shù)資料
型號： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁數(shù)： 35/106頁
文件大?。?/td> 605K
代理商： TSB12LV01BPZ
2
–
19
2.2.14
Header1 Register at 3Ch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
Destination ID
Header1 register must contain the isochronous header or the second quadlet of an asynchronous header
if in header insert mode. If not in header insert mode or if in receive mode, this register will be updated with
the received header. This register powers up with all bits reset to 0. For multiple isochronous packets (within
the same isochronous cycle), this register would contain the isochronous header of the second isochronous
packet in the same format as the header0 register, if in header insert mode. This register is write protected
such that it cannot be written to unless automatic header insert mode is enabled and DM is in transmit mode
(i.e., DMHDR=0 and DMRX=0).
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
–
15
DestinationID
Destination ID
R/W
For asynchronous packets this field contains the destination
nodes ID.
16
–
31
RESERVED
Header2 Register at 40h
Reserved
2.2.15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
HEADER2
Header2 register must contain the isochronous header or the third quadlet of a asynchronous header if in
header insert mode. If not in header insert mode or if in receive mode, this register will be updated with the
received header. This register powers up with all bits reset to 0. For multiple isochronous packets (within
the same isochronous cycle), this register would contain the isochronous header of the third isochronous
packet in the same format as the header0 register, if in header insert mode. This register is write protected
such that it cannot be written to unless automatic header insert mode is enabled and in transmit mode (i.e.,
DMHDR=0 and DMRX=0).
BIT
NUMBER
BIT NAME
DIR
DESCRIPTION
0
–
31
Header2
R/W
Header quadlet for asynchronous or isochronous packet.
2.2.16
Header3 Register at 44h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
HEADER3
Header3 register must contain the isochronous header or the fourth quadlet of an asynchronous header if
in header insert mode. If not in header insert mode or if in receive mode, this register will be updated with
the received header. This register powers up with all bits reset to 0. For multiple isochronous packets (within
the same isochronous cycle), this register would contain the isochronous header of the fourth isochronous
packet in the same format as the header0 register, if in header insert mode. This register is write protected
such that it cannot be written to unless automatic header insert mode is enabled and DM is in transmit mode
(i.e., DMHDR=0 and DMRX=0).
BIT
NUMBER
BIT NAME
DIR
DESCRIPTION
0
–
31
Header3
R/W
Header quadlet for asynchronous or isochronous packet.
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相關代理商/技術參數(shù)
參數(shù)描述
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01PZ 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB12LV21 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21A 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE
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