參數(shù)資料
型號(hào)： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁(yè)數(shù)： 69/106頁(yè)
文件大?。?/td> 605K
代理商： TSB12LV01BPZ
5
–
13
5.2.3
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence
of operations are performed:
Isochronous Packet Receive Without Header and Trailer
Step 1:
The packet router control logic will route the packet to the data mover. If the sync bit field
in the header quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port
register at 18h, DMPRE will be asserted high for one DMCLK cycle.
After the header is sent through, DMDONE will be asserted high for one DMCLK cycle.
DMRW is then asserted high as the data payload comes through.
After all data has been received on the DMD[0:15] lines, DMRW will be asserted low and
the trailer quadlet will then come out on the DMD[0:15] lines.
PKTFLAG is never asserted high in this mode. Figure 5
–
17 shows the timing diagram for this mode at
400 Mbps. Figure 5
–
17 shows the case where DMPRE is asserted high for one DMCLK cycle to indicate
that the sync bits of the received isochronous header matches the contents of the ISYNCRCVN field.
Step 2:
Step 3:
Trailer quadlet
Header quadlet
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
DMPRE
Figure 5
–
17. Isochronous Receive Without Header and Trailer
Isochronous Packet Receive With Header and Trailer
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence
of operations are performed:
5.2.4
Step 1:
The packet router control logic will route the packet to the data mover. If the sync bit field
in the header quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port
register at 18h, DMPRE will be asserted high for one DMCLK cycle. At the same time
DMDONE will be asserted high for one DMCLK cycle.
This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only
asserted high when the header quadlet is being received.
After all the data payload has been received on the DMD[0:15] lines, PKTFLAG will be
asserted high again as the trailer quadlet is being received. Once the entire packet is
received, the DMRW line will be asserted low.
Figure 5
–
18 shows the timing diagram for this mode at 400 Mbps. Also, Figure 5
–
18 shows the case where
DMPRE is asserted high for one DMCLK cycle to indicate that the sync bits of the received isochronous
header matches the contents of the ISYNCRCVN field.
Step 2:
Step 3:
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
DMPRE
Trailer quadlet
Header quadlet
Figure 5
–
18. Isochronous Receive With Header and Trailer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01PZ 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB12LV21 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21A 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE
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