參數(shù)資料
型號(hào)： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁(yè)數(shù)： 44/106頁(yè)
文件大?。?/td> 605K
代理商： TSB12LV01BPZ
3
–
7
3.3.2
Byte and word fixed-timing reads shown in Figure 3
–
7 and Figure 3
–
8. Fixed-timing mode supports burst
transfers. If MCS is asserted low for more than one BCLK cycle, burst mode is enabled. The fixed-timing
burst mode does not have a limit on the maximum burst size allowed.
Microcontroller Fixed-Timing Mode
The timing sequence in the fixed-timing a read transaction can be summarized as follows:
1.
The host pulses MCS low to signal the start of access. Pulsing MCS low for more than once clock
cycle will enable burst mode. The number of BCLK cycles during which MCS is asserted low
determines the burst size.
2.
When the rising edge of BCLK samples MCS low and MWR high, the register value or GRF data
pointed to by MA is latched onto the MD lines. The MD lines will latch on every rising edge of BCLK
if MCS is asserted low.
3.
After 2 BCLK cycles, the TSB12LV32 pulses MCA low for one clock cycle to signal the completion
of the requested operation. If MCS is pulsed low for
n
BCLK cycles, MCA will also be pulsed low
for
n
cycles. Note that MA needs only contain valid data during the first cycle in which MCS is low.
Except for the first one, every data transfer takes only one BCLK cycle. If a read transaction is
accessing the CFR, it may not cross any register boundary.
Another read or write transaction can begin after the next rising edge of BCLK. Note that data size is
determined by the MCMODE/SIZ1 and M8BIT/SIZ0 signals. The ColdFire signal is only asserted high when
the micro interface is operating in ColdFire mode.
BCLK
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A1
A2
D1
D2
D3
D4
D5
Figure 3
–
7. Byte Fixed-Timing Read
相關(guān)PDF資料
PDF描述
TSB12LV26-EP 672-pin FineLine BGA
TSB12LV22PZP OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26PZ OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB14AA1 FPGA (Field-Programmable Gate Array)
TSB14AA1I FPGA (Field-Programmable Gate Array)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01PZ 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB12LV21 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21A 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*