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參數(shù)資料
| 型號(hào)： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 178/268頁(yè) |
| 文件大小： | 1289K |
| 代理商： | ARM7TDMI |
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Coprocessor Interface
ARM7TDMI Data Sheet
ARM DDI 0029E
7-2
O
7.1
Overview
The functionality of the ARM7TDMI instruction set may be extended by the addition of
up to 16 external coprocessors. When the coprocessor is not present, instructions
intended for it will trap, and suitable software may be installed to emulate its functions.
Adding the coprocessor will then increase the system performance in a software
compatible way. Note that some coprocessor numbers have already been assigned.
Contact ARM Ltd for up-to-date information.
7.2
Interface Signals
Three dedicated signals control the coprocessor interface,
nCPI
,
CPA
and
CPB
. The
CPA
and
CPB
inputs should be driven HIGH except when they are being used for
handshaking.
7.2.1 Coprocessor present/absent
ARM7TDMI takes
nCPI
LOW whenever it starts to execute a coprocessor (or
undefined) instruction. (This will not happen if the instruction fails to be executed
because of the condition codes.) Each coprocessor will have a copy of the instruction,
and can inspect the CP# field to see which coprocessor it is for. Every coprocessor in
a system must have a unique number and if that number matches the contents of the
CP# field the coprocessor should drive the
CPA
(coprocessor absent) line LOW. If no
coprocessor has a number which matches the CP# field,
CPA
and
CPB
will remain
HIGH, and ARM7TDMI will take the undefined instruction trap. Otherwise ARM7TDMI
observes the
CPA
line going LOW, and waits until the coprocessor is not busy.
7.2.2 Busy-waiting
If
CPA
goes LOW, ARM7TDMI will watch the
CPB
(coprocessor busy) line. Only the
coprocessor which is driving
CPA
LOW is allowed to drive
CPB
LOW, and it should do
so when it is ready to complete the instruction. ARM7TDMI will busy-wait while
CPB
is HIGH, unless an enabled interrupt occurs, in which case it will break off from the
coprocessor handshake to process the interrupt. Normally ARM7TDMI will return from
processing the interrupt to retry the coprocessor instruction.
When
CPB
goes LOW, the instruction continues to completion. This will involve data
transfers taking place between the coprocessor and either ARM7TDMI or memory,
except in the case of coprocessor data operations which complete immediately the
coprocessor ceases to be busy.
All three interface signals are sampled by both ARM7TDMI and the coprocessor(s) on
the rising edge of
MCLK
. If all three are LOW, the instruction is committed to
execution, and if transfers are involved they will start on the next cycle. If
nCPI
has
gone HIGH after being LOW, and before the instruction is committed, ARM7TDMI has
broken off from the busy-wait state to service an interrupt. The instruction may be
restarted later, but other coprocessor instructions may come sooner, and the
instruction should be discarded.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS1431 | Precision Adjustable Shunt Reference |
| AS1431DR4LP13 | Precision Adjustable Shunt Reference |
| AS1431DR4LP7 | Precision Adjustable Shunt Reference |
| AS1431DR4LPA | Precision Adjustable Shunt Reference |
| AS1431DR4LPB | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM7TDMI_G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM920T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System-on-Chip Platform OS Processor |
| ARM940T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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