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參數(shù)資料
| 型號(hào)： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 30/268頁(yè) |
| 文件大小： | 1289K |
| 代理商： | ARM7TDMI |
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Programmers Model
ARM7TDMI Data Sheet
ARM DDI 0029E
3-4
O
3.6
Operating Modes
ARM7TDMI supports seven modes of operation:
User (usr):
The normal ARM program execution state
FIQ (fiq):
Designed to support a data transfer or channel process
IRQ (irq):
Used for general-purpose interrupt handling
Supervisor (svc):
Protected mode for the operating system
Abort mode (abt):
Entered after a data or instruction prefetch abort
System (sys):
A privileged user mode for the operating system
Undefined (und):
Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by
external interrupts or exception processing. Most application programs will execute in
User mode. The non-user modes - known as
privileged modes
- are entered in order
to service interrupts or exceptions, or to access protected resources.
3.7
Registers
ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six
status registers - but these cannot all be seen at once. The processor state and
operating mode dictate which registers are available to the programmer.
3.7.1 The ARM state register set
In ARM state, 16 general registers and one or two status registers are visible at any
one time. In privileged (non-User) modes, mode-specific banked registers are
switched in.
·
Figure 3-3: Register organization in ARM state
shows which registers
are available in each mode: the banked registers are marked with a shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All of
these except R15 are general-purpose, and may be used to hold either data or
address values. In addition to these, there is a seventeenth register used to store
status information
Register 14
is used as the subroutine link register. This receives a copy of
R15 when a Branch and Link (BL) instruction is executed. At
all other times it may be treated as a general-purpose
register. The corresponding banked registers R14_svc,
R14_irq, R14_fiq, R14_abt and R14_und are similarly used
to hold the return values of R15 when interrupts and
exceptions arise, or when Branch and Link instructions are
executed within interrupt or exception routines.
Register 15
holds the Program Counter (PC). In ARM state, bits [1:0] of
R15 are zero and bits [31:2] contain the PC. In THUMB state,
bit [0] is zero and bits [31:1] contain the PC.
Register 16
is the CPSR (Current Program Status Register). This
contains condition code flags and the current mode bits.
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| ARM7TDMI_G | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
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| ARM940T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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