
ARM Instruction Set - B, BL
ARM7TDMI Data Sheet
ARM DDI 0029E
4-8
O
4.4
Branch and Branch with Link (B, BL)
The instruction is only executed if the condition is true. The various conditions are
defined
·
Table 4-2: Condition code summary
on page 4-5. The instruction encoding
is shown in
·
Figure 4-3: Branch instructions
, below.
Figure 4-3: Branch instructions
Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left
two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore
specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch
operation, which causes the PC to be 2 words (8 bytes) ahead of the current
instruction.
Branches beyond +/- 32Mbytes must use an offset or absolute destination which has
been previously loaded into a register. In this case the PC should be manually saved
in R14 if a Branch with Link type operation is required.
4.4.1 The link bit
Branch with Link (BL) writes the old PC into the link register (R14) of the current bank.
The PC value written into R14 is adjusted to allow for the prefetch, and contains the
address of the instruction following the branch and link instruction. Note that the CPSR
is not saved with the PC and R14[1:0] are always cleared.
To return from a routine called by Branch with Link use MOV PC,R14 if the link register
is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed
to by Rn.
4.4.2 Instruction cycle times
Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S
and N are as defined in
·
6.2 Cycle Types
on page 6-2.
Cond
101
L
offset
31
28 27
25 24 23
0
Link bit
0 = Branch
1 = Branch with Link
Condition field