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Programmers Model
ARM7TDMI Data Sheet
ARM DDI 0029E
3-8
O
3.8
The Program Status Registers
The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved
Program Status Registers (SPSRs) for use by exception handlers. These registers
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode
The arrangement of bits is shown in
·
Figure 3-6: Program status register format
.
Figure 3-6: Program status register format
3.8.1 The condition code flags
The N, Z, C and V bits are the condition code flags. These may be changed as a result
of arithmetic and logical operations, and may be tested to determine whether an
instruction should be executed.
In ARM state, all instructions may be executed conditionally: see
·
4.2 The Condition
Field
on page 4-5 for details.
In THUMB state, only the Branch instruction is capable of conditional execution: see
·
5.17 Format 17: software interrupt
on page 5-38
3.8.2 The control bits
The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as
the control bits. These will change when an exception arises. If the processor is
operating in a privileged mode, they can also be manipulated by software.
The T bit
This reflects the operating state. When this bit is set, the
processor is executing in THUMB state, otherwise it is
executing in ARM state. This is reflected on the
TBIT
external signal.
Note that the software must never change the state of the
TBIT
in the CPSR. If this happens, the processor will
enter an unpredictable state.
0
1
2
3
4
5
6
7
8
27
28
29
30
31
M0
M1
M2
M3
M4
.
F
I
V
C
Z
N
Overflow
Carry / Borrow
/ Extend
Zero
Negative / Less Than
Mode bits
State bit
FIQ disable
IRQ disable
.
.
condition code flags
control bits
(reserved)
23
.
.
24
T
25
.
26
.