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| 型號(hào)： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 223/268頁(yè) |
| 文件大?。?/td> | 1289K |
| 代理商： | ARM7TDMI |
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ICEBreaker Module
ARM7TDMI Data Sheet
ARM DDI 0029E
9-13
O
The
RANGEOUT
output of watchpoint register 1 provides the
RANGE
input to
watchpoint register 0. This allows two breakpoints to be coupled together to form
range breakpoints. Note that selectable ranges are restricted to being powers of 2.
This is best illustrated by an example.
Example
If a breakpoint is to occur when the address is in the first 256 bytes of memory, but not
in the first 32 bytes, the watchpoint registers should be programmed as follows:
1
Watchpoint 1 is programmed with an address value of 0x00000000 and an
address mask of 0x0000001F. The ENABLE bit is cleared. All other
Watchpoint 1 registers are programmed as normal for a breakpoint. An
address within the first 32 bytes will cause the RANGE output to go HIGH but
the breakpoint will not be triggered.
2
Watchpoint 0 is programmed with an address value of 0x00000000 and an
address mask of 0x000000FF. The ENABLE bit is set and the RANGE bit
programmed to match a 0. All other Watchpoint 0 registers are programmed
as normal for a breakpoint.
If Watchpoint 0 matches but Watchpoint 1 does not (ie the
RANGE
input to Watchpoint
0 is 0), the breakpoint will be triggered.
9.8
Disabling ICEBreaker
ICEBreaker may be disabled by wiring the
DBGEN
input LOW.
When
DBGEN
is LOW,
BREAKPT
and
DBGRQ
to the core are forced LOW,
DBGACK
from the ARM7TDMI is also forced LOW and the
IFEN
input to the core is
forced HIGH, enabling interrupts to be detected by ARM7TDMI.
When
DBGEN
is LOW, ICEBreaker is also put into a low-power mode.
9.9
ICEBreaker Timing
The
EXTERN1
and
EXTERN0
inputs are sampled by ICEBreaker on the falling edge
of
ECLK
. Sufficient set-up and hold time must therefore be allowed for these signals.
9.10 Programming Restriction
The ICEBreaker watchpoint units should only be programmed when the clock to the
core is stopped. This can be achieved by putting the core into the debug state.
The reason for this restriction is that if the core continues to run at
ECLK
rates when
ICEBreaker is being programmed at
TCK
rates, it is possible for the
BREAKPT
signal
to be asserted asynchronously to the core.
This restriction does not apply if
MCLK
and
TCK
are driven from the same clock, or if
it is known that the breakpoint or watchpoint condition can only occur some time after
ICEBreaker has been programmed.
Note
This restriction does not apply in any event to the Debug Control or Status Registers.
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| AS1431 | Precision Adjustable Shunt Reference |
| AS1431DR4LP13 | Precision Adjustable Shunt Reference |
| AS1431DR4LP7 | Precision Adjustable Shunt Reference |
| AS1431DR4LPA | Precision Adjustable Shunt Reference |
| AS1431DR4LPB | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM7TDMI_G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM920T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System-on-Chip Platform OS Processor |
| ARM940T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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