Debug Interface
ARM7TDMI Data Sheet
ARM DDI 0029E
8-23
O
It can be seen from
·
Figure 8-2: Debug state entry
on page 8-4 that the final memory
access occurs in the cycle
after
DBGACK
goes HIGH, and this is the point at which
the cycle counter should be disabled.
·
Figure 8-7: Debug exit sequence
shows that
the first memory access that the cycle counter has not seen before occurs in the cycle
after
DBGACK
goes LOW, and so this is the point at which the counter should be re-
enabled.
Note that when a system speed access from debug state occurs, ARM7TDMI
temporarily drops out of debug state, and so
DBGACK
can go LOW. If there are
peripherals which are sensitive to the number of memory accesses, they must be led
to believe that ARM7TDMI is still in debug state. By programming the ICEBreaker
control register, the value on
DBGACK
can be forced to be HIGH. See
·
Chapter 9,
ICEBreaker Module
for more details.
8.12 The PC’s Behaviour During Debug
In order that ARM7TDMI may be forced to branch back to the place at which program
flow was interrupted by debug, the debugger must keep track of what happens to the
PC. There are five cases: breakpoint, watchpoint, watchpoint when another exception
occurs, debug request and system speed access.
8.12.1 Breakpoint
Entry to the debug state from a breakpoint advances the PC by 4 addresses, or 16
bytes. Each instruction executed in debug state advances the PC by 1 address, or 4
bytes. The normal way to exit from debug state after a breakpoint is to remove the
breakpoint, and branch back to the previously breakpointed address.
For example, if ARM7TDMI entered debug state from a breakpoint set on a given
address and 2 debug speed instructions were executed, a branch of -7 addresses
must occur (4 for debug entry, +2 for the instructions, +1 for the final branch). The
following sequence shows the data scanned into scan chain 1. This is msb first, and
so the first digit is the value placed in the
BREAKPT
bit, followed by the instruction
data.
0 E0802000; ADD R2, R0, R0
1 E1826001; ORR R6, R2, R1
0 EAFFFFF9; B -7 (2’s complement)
Note that once in debug state, a minimum of two instructions must be executed before
the branch, although these may both be NOPs (MOV R0, R0). For small branches, the
final branch could be replaced with a subtract with the PC as the destination (SUB PC,
PC, #28 in the above example).
8.12.2 Watchpoints
Returning to program execution after entering debug state from a watchpoint is done
in the same way as the procedure described above. Debug entry adds 4 addresses to
the PC, and every instruction adds 1 address. The difference is that since the
instruction that caused the watchpoint has executed, the program returns to the next
instruction.