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參數(shù)資料
| 型號(hào)： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 180/268頁(yè) |
| 文件大?。?/td> | 1289K |
| 代理商： | ARM7TDMI |
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Coprocessor Interface
ARM7TDMI Data Sheet
ARM DDI 0029E
7-4
O
7.5
Idempotency
A consequence of the implementation of the coprocessor interface, with the
interruptible busy-wait state, is that all instructions may be interrupted at any point up
to the time when the coprocessor goes not-busy. If so interrupted, the instruction will
normally be restarted from the beginning after the interrupt has been processed. It is
therefore essential that any action taken by the coprocessor before it goes not-busy
must be idempotent, ie must be repeatable with identical results.
For example, consider a FIX operation in a floating point coprocessor which returns
the integer result to an ARM7TDMI register. The coprocessor must stay busy while it
performs the floating point to fixed point conversion, as ARM7TDMI will expect to
receive the integer value on the cycle immediately following that where it goes not-
busy. The coprocessor must therefore preserve the original floating point value and
not corrupt it during the conversion, because it will be required again if an interrupt
arises during the busy period.
The coprocessor data operation class of instruction is not generally subject to
idempotency considerations, as the processing activity can take place after the
coprocessor goes not-busy. There is no need for ARM7TDMI to be held up until the
result is generated, because the result is confined to stay within the coprocessor.
7.6
Undefined Instructions
Undefined instructions are treated by ARM7TDMI as coprocessor instructions. All
coprocessors must be absent (ie
CPA
and
CPB
must be HIGH) when an undefined
instruction is presented. ARM7TDMI will then take the undefined instruction trap. Note
that the coprocessor need only look at bit 27 of the instruction to differentiate
undefined instructions (which all have 0 in bit 27) from coprocessor instructions (which
all have 1 in bit 27)
Note that when in THUMB state, coprocessor instructions are not supported but
undefined instructions are. Thus, all coprocessors must monitor the state of the
TBIT
output from ARM7TDMI. When ARM7TDMI is in THUMB state, coprocessors must
appear absent (ie they must drive
CPA
and
CPB
HIGH) and the instructions seen on
the data bus must be ignored. In this way, coprocessors will not erroneously execute
THUMB instructions, and all undefined instructions will be handled correctly.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS1431 | Precision Adjustable Shunt Reference |
| AS1431DR4LP13 | Precision Adjustable Shunt Reference |
| AS1431DR4LP7 | Precision Adjustable Shunt Reference |
| AS1431DR4LPA | Precision Adjustable Shunt Reference |
| AS1431DR4LPB | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM7TDMI_G | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM920T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:System-on-Chip Platform OS Processor |
| ARM940T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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