ARM Instruction Set - LDC, STC
ARM7TDMI Data Sheet
ARM DDI 0029E
4-53
O
4.15 Coprocessor DataTransfers (LDC, STC)
The instruction is only executed if the condition is true. The various conditions are
defined in
·
Table 4-2: Condition code summary
on page 4-5. The instruction encoding
is shown in
·
Figure 4-26: Coprocessor data transfer instructions
.
This class of instruction is used to load (LDC) or store (STC) a subset of a
coprocessors’s registers directly to memory. ARM7TDMI is responsible for supplying
the memory address, and the coprocessor supplies or accepts the data and controls
the number of words transferred.
Figure 4-26: Coprocessor data transfer instructions
4.15.1 The coprocessor fields
The CP# field is used to identify the coprocessor which is required to supply or accept
the data, and a coprocessor will only respond if its number matches the contents of
this field.
The CRd field and the N bit contain information for the coprocessor which may be
interpreted in different ways by different coprocessors, but by convention CRd is the
register to be transferred (or the first register where more than one is to be
transferred), and the N bit is used to choose one of two transfer length options. For
instance N=0 could select the transfer of a single register, and N=1 could select the
transfer of all the registers for context switching.
Cond
Rn
0
11
12
15
16
19
20
21
24
25
27
28
31
P U
W L
22
23
110
N
CRd
CP#
Offset
7
8
Coprocessor number
Coprocessor source/destination register
Unsigned 8 bit immediate offset
Base register
Load/Store bit
0 = Store to memory
1 = Load from memory
Write-back bit
0 = no write-back
1 = write address into base
Transfer length
Pre/Post indexing bit
1 = pre; add offset before transfer
Up/Down bit
1 = up; add offset to base
Condition field