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參數(shù)資料
| 型號： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁數(shù)： | 201/268頁 |
| 文件大?。?/td> | 1289K |
| 代理商： | ARM7TDMI |
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Debug Interface
ARM7TDMI Data Sheet
ARM DDI 0029E
8-21
O
8.11.2 Determining system state
In order to meet the dynamic timing requirements of the memory system, any attempt
to access system state must occur synchronously to it. Thus, ARM7TDMI must be
forced to synchronise back to system speed. This is controlled by the 33rd bit of scan
chain 1.
Any instruction may be placed in scan chain 1 with bit 33 (the
BREAKPT
bit) LOW.
This instruction will then be executed at debug speed. To execute an instruction at
system speed, the instruction prior to it must be scanned into scan chain 1 with bit 33
set HIGH.
After the system speed instruction has been scanned into the data bus and clocked
into the pipeline, the BYPASS instruction must be loaded into the TAP controller. This
will cause ARM7TDMI to automatically synchronise back to
MCLK
(the system clock),
execute the instruction at system speed, and then re-enter debug state and switch
itself back to the internally generated
DCLK
. When the instruction has completed,
DBGACK
will be HIGH and the core will have switched back to
DCLK
. At this point,
INTEST can be selected in the TAP controller, and debugging can resume.
In order to determine that a system speed instruction has completed, the debugger
must look at both
DBGACK
and
nMREQ
. In order to access memory, ARM7TDMI
drives
nMREQ
LOW after it has synchronised back to system speed. This transition is
used by the memory controller to arbitrate whether ARM7TDMI can have the bus in
the next cycle. If the bus is not available, ARM7TDMI may have its clock stalled
indefinitely. Therefore, the only way to tell that the memory access has completed, is
to examine the state of both
nMREQ
and
DBGACK
. When both are HIGH, the access
has completed. Usually, the debugger would be using ICEBreaker to control
debugging, and by reading ICEBreaker's status register, the state of
nMREQ
and
DBGACK
can be determined. Refer to
·
Chapter 9, ICEBreaker Module
for more
details.
By the use of system speed load multiples and debug speed store multiples, the state
of the system’s memory can be fed back to the debug host.
There are restrictions on which instructions may have the 33rd bit set. The only valid
instructions on which to set this bit are loads, stores, load multiple and store multiple.
See also
·
8.11.3 Exit from debug state
. When ARM7TDMI returns to debug state
after a system speed access, bit 33 of scan chain 1 is set HIGH. This gives the
debugger information about why the core entered debug state the first time this scan
chain is read.
8.11.3 Exit from debug state
Leaving debug state involves restoring ARM7TDMI’s internal state, causing a branch
to the next instruction to be executed, and synchronising back to
MCLK
. After
restoring internal state, a branch instruction must be loaded into the pipeline. See
·
8.12 The PC’s Behaviour During Debug
on page 8-23 for details on calculating the
branch.
Bit 33 of scan chain 1 is used to force ARM7TDMI to resynchronise back to
MCLK
.
The penultimate instruction of the debug sequence is scanned in with bit 33 set HIGH.
The final instruction of the debug sequence is the branch, and this is scanned in with
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| ARM7TDMI_G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
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| ARM940T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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