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參數(shù)資料
| 型號： | ARM7TDMI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | general purpose 32-bit microprocessors |
| 中文描述： | 通用32位微處理器 |
| 文件頁數(shù)： | 179/268頁 |
| 文件大?。?/td> | 1289K |
| 代理商： | ARM7TDMI |
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Coprocessor Interface
ARM7TDMI Data Sheet
ARM DDI 0029E
7-3
O
7.2.3 Pipeline following
In order to respond correctly when a coprocessor instruction arises, each coprocessor
must have a copy of the instruction. All ARM7TDMI instructions are fetched from
memory via the main data bus, and coprocessors are connected to this bus, so they
can keep copies of all instructions as they go into the ARM7TDMI pipeline. The
nOPC
signal indicates when an instruction fetch is taking place, and
MCLK
gives the timing
of the transfer, so these may be used together to load an instruction pipeline within the
coprocessor.
7.2.4 Data transfer cycles
Once the coprocessor has gone not-busy in a data transfer instruction, it must supply
or accept data at the ARM7TDMI bus rate (defined by
MCLK
). It can deduce the
direction of transfer by inspection of the L bit in the instruction, but must only drive the
bus when permitted to by
DBE
being HIGH. The coprocessor is responsible for
determining the number of words to be transferred; ARM7TDMI will continue to
increment the address by one word per transfer until the coprocessor tells it to stop.
The termination condition is indicated by the coprocessor driving
CPA
and
CPB
HIGH.
There is no limit in principle to the number of words which one coprocessor data
transfer can move, but by convention no coprocessor should allow more than 16
words in one instruction. More than this would worsen the worst case ARM7TDMI
interrupt latency, as the instruction is not interruptible once the transfers have
commenced. At 16 words, this instruction is comparable with a block transfer of 16
registers, and therefore does not affect the worst case latency.
7.3
Register Transfer Cycle
The coprocessor register transfer cycle is the one case when ARM7TDMI requires the
data bus without requiring the memory to be active. The memory system is informed
that the bus is required by ARM7TDMI taking both
nMREQ
and
SEQ
HIGH. When the
bus is free,
DBE
should be taken HIGH to allow ARM7TDMI or the coprocessor to
drive the bus, and an
MCLK
cycle times the transfer.
7.4
Privileged Instructions
The coprocessor may restrict certain instructions for use in privileged modes only. To
do this, the coprocessor will have to track the
nTRANS
output.
As an example of the use of this facility, consider the case of a floating point
coprocessor (FPU) in a multi-tasking system. The operating system could save all the
floating point registers on every task switch, but this is inefficient in a typical system
where only one or two tasks will use floating point operations. Instead, there could be
a privileged instruction which turns the FPU on or off. When a task switch happens,
the operating system can turn the FPU off without saving its registers. If the new task
attempts an FPU operation, the FPU will appear to be absent, causing an undefined
instruction trap. The operating system will then realise that the new task requires the
FPU, so it will re-enable it and save FPU registers. The task can then use the FPU as
normal. If, however, the new task never attempts an FPU operation (as will be the case
for most tasks), the state saving overhead will have been avoided.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS1431 | Precision Adjustable Shunt Reference |
| AS1431DR4LP13 | Precision Adjustable Shunt Reference |
| AS1431DR4LP7 | Precision Adjustable Shunt Reference |
| AS1431DR4LPA | Precision Adjustable Shunt Reference |
| AS1431DR4LPB | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM7TDMI_G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Technical Reference Manual |
| ARM7TDMI-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔 |
| ARM920T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System-on-Chip Platform OS Processor |
| ARM940T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TECHNICAL REFERENCE MANUAL |
| ARM946E-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM946E-S Microprocessor Core with Cache technical manual 6/01 |
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