參數資料
型號: DK-DEV-2AGX125N
廠商: Altera
文件頁數: 22/90頁
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產品培訓模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產品: Arria? II GX FPGA Development Kit
標準包裝: 1
系列: Arria II GX
類型: FPGA
適用于相關產品: EP2AGX125EF35
所含物品: 板,線纜,CD,DVD,電源
產品目錄頁面: 605 (CN2011-ZH PDF)
相關產品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱: 544-2600
Ch
ap
te
r
1:
De
vice
Da
ta
sh
e
tfo
r
Arria
II
De
vice
s
1–2
1
Switc
h
ing
C
h
ar
acter
istics
Dec
ember
2013
Alte
ra
Cor
p
oration
A
Switching Characteristics
This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks for commercial grade
devices. The following tables are considered final and are based on actual silicon characterization and testing. These numbers
reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions.
Transceiver Performance Specifications
Table 1–34 lists the Arria II GX transceiver specifications.
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 1 of 7)
Symbol/
Description
Condition
I3
C4
C5 and I5
C6
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL
Input frequency
from REFCLK
input pins
50
622.08
50
622.08
50
622.08
50
622.08
MHz
Input frequency
from PLD input
50
200
50
200
50
200
50
200
MHz
Absolute VMAX
for a REFCLK pin
2.2
2.2
2.2
2.2
V
Absolute VMIN for
a REFCLK pin
–0.3
–0.3
–0.3
–0.3
V
Rise/fall time (2)
0.2
0.2
0.2
0.2
UI
Duty cycle
45
55
45
55
45
55
45
55
%
Peak-to-peak
differential input
voltage
200
2000
200
2000
200
2000
200
2000
mV
Spread-spectrum
modulating clock
frequency
PCIe
30
33
30
33
30
33
30
33
kHz
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