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| 型號(hào)： | DK-DEV-2AGX125N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 70/90頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV ARRIA II GX FPGA 2AGX125 |
| 產(chǎn)品培訓(xùn)模塊： | Arria II GX FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 特色產(chǎn)品： | Arria? II GX FPGA Development Kit |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Arria II GX |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | EP2AGX125EF35 |
| 所含物品： | 板，線纜，CD，DVD，電源 |
| 產(chǎn)品目錄頁(yè)面： | 605 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG 544-2598-5-ND - IC ARRIA II GX 125K 1152FBG 544-2597-5-ND - IC ARRIA II GX 125K 1152FBG |
| 其它名稱： | 544-2600 |
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1–64
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Table 1–54 lists the high-speed I/O timing for Arria II GZ devices.
fHSDR (data rate)
SERDES factor
J = 3 to 10
945
945
740
640
Mbps
SERDES factor
J = 2 (using
DDR registers)
Mbps
SERDES factor
J = 1 (using
SDR registers)
Mbps
Soft-CDR PPM
tolerance
Soft-CDR
mode
—
300
—
300
—
300
—
300
PPM
DPA run length
DPA mode
—
10,000
—
10,000
—
10,000
—
10,000
UI
Sampling
window (SW)
Non-DPA mode
—
300
—
300
—
350
—
400
ps
Notes to Table 1–53:
(1) fHSCLK_IN = fHSDR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate.
(2) Applicable for interfacing with DPA receivers only. For interfacing with non-DPA receivers, you must calculate the leftover timing margin in the
receiver by performing link timing closure analysis. For Arria II GX transmitter to Arria II GX non-DPA receiver, the maximum supported data
rate is 945 Mbps. For data rates above 840 Mbps, perform PCB trace compensation by adjusting the PCB trace length for LVDS channels to
improve channel-to-channel skews.
(3) The minimum and maximum specification depends on the clock source (for example, PLL and clock pin) and the clock routing resource you
use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate.
(4) The specification is only applicable under the influence of core noise.
(5) Applicable for true LVDS using dedicated SERDES only.
(6) Dedicated SERDES and DPA features are only available on the right banks.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin.
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 4 of 4)
Symbol
Conditions
I3
C4
C5,I5
C6
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 1 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
Clock
fHSCLK_in (input clock
frequency) true
differential I/O
standards
Clock boost factor
W = 1 to 40 (3)
5
—
717
5
—
717
MHz
fHSCLK_in (input clock
frequency) single
ended I/O standards
Clock boost factor
W = 1 to 40 (3)
5
—
717
5
—
717
MHz
fHSCLK_in (input clock
frequency) single
ended I/O standards
Clock boost factor
W = 1 to 40 (3)
5
—
420
5
—
420
MHz
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