參數(shù)資料
型號(hào): DK-DEV-2AGX125N
廠商: Altera
文件頁(yè)數(shù): 25/90頁(yè)
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝: 1
系列: Arria II GX
類(lèi)型: FPGA
適用于相關(guān)產(chǎn)品: EP2AGX125EF35
所含物品: 板,線(xiàn)纜,CD,DVD,電源
產(chǎn)品目錄頁(yè)面: 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱(chēng): 544-2600
Ch
ap
te
r
1:
De
vice
Da
ta
sh
e
tfo
r
Arria
II
De
vice
s
1–2
3
Switc
h
ing
C
h
ar
acter
istics
Dec
ember
2013
Alte
ra
Cor
p
oration
A
fixedclk
clock
frequency
PCIe
Receiver
Detect
125
125
125
125
MHz
reconfig_
clk
clock
frequency
Dynamic
reconfig.
clock
frequency
2.5/
37.5
—50
2.5/
37.5
—50
2.5/
37.5
—50
2.5/
37.5
—50
MHz
Delta time
between
reconfig_
clks
——
2
2
2
2
ms
Transceiver block
minimum
power-down
pulse width
——
1
1
1
1
s
Receiver
Supported I/O
Standards
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
600
6375
600
3750
600
3750
600
3125
Mbps
Absolute VMAX
for a receiver pin
1.5
1.5
1.5
1.5
V
Absolute VMIN for
a receiver pin
-0.4
-0.4
-0.4
-0.4
V
Maximum
peak-to-peak
differential input
voltage VID (diff
p-p)
VICM = 0.82 V
setting
2.7
2.7
2.7
2.7
V
VICM =1.1 V
setting (7)
1.6
1.6
1.6
1.6
V
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 3 of 7)
Symbol/
Description
Condition
I3
C4
C5 and I5
C6
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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