參數資料
型號: DK-DEV-2AGX125N
廠商: Altera
文件頁數: 33/90頁
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產品培訓模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產品: Arria? II GX FPGA Development Kit
標準包裝: 1
系列: Arria II GX
類型: FPGA
適用于相關產品: EP2AGX125EF35
所含物品: 板,線纜,CD,DVD,電源
產品目錄頁面: 605 (CN2011-ZH PDF)
相關產品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱: 544-2600
Chapter 1: Device Datasheet for Arria II Devices
1–31
Switching Characteristics
December 2013
Altera Corporation
Transmitter
Supported I/O Standards
1.5-V PCML
Data rate (14)
600
6375
600
3750
Mbps
VOCM
0.65 V setting
650
650
mV
Differential on-chip
termination resistors
85
setting
85 ± 15%
100
setting
100 ± 15%
120
setting
120 ± 15%
150-
setting
150 ± 15%
Differential and common
mode return loss
PCIe Gen1 and
Gen2 (TX VOD=4),
XAUI (TX VOD=6),
HiGig+
(TX VOD=6),
CEI SR/LR
(TX VOD=8),
SRIO SR (VOD=6),
SRIO LR (VOD=8),
CPRI LV (VOD=6),
CPRI HV (VOD=2),
OBSAI (VOD=6),
SATA (VOD=4),
Compliant
Rise time (15)
50
200
50
200
ps
Fall time (15)
50
200
50
200
ps
Intra-differential pair skew
15
15
ps
Intra-transceiver block
transmitter
channel-to-channel skew
×4 PMA and PCS
bonded mode
Example: XAUI,
PCIe ×4, Basic ×4
——
120
—120
ps
Inter-transceiver block
transmitter
channel-to-channel skew
×8 PMA and PCS
bonded mode
Example: PCIe ×8,
Basic ×8
——
500
—500
ps
CMU0 PLL and CMU1 PLL
Supported Data Range
600
6375
600
3750
Mbps
pll_powerdown
minimum
pulse width
(tpll_powerdown)
—1
1
s
CMU PLL lock time from
pll_powerdown
de-assertion
100
100
s
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 4 of 5)
Symbol/
Description
Conditions
–C3 and –I3 (1)
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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