參數(shù)資料
型號(hào): DK-DEV-2AGX125N
廠商: Altera
文件頁(yè)數(shù): 71/90頁(yè)
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝: 1
系列: Arria II GX
類(lèi)型: FPGA
適用于相關(guān)產(chǎn)品: EP2AGX125EF35
所含物品: 板,線(xiàn)纜,CD,DVD,電源
產(chǎn)品目錄頁(yè)面: 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱(chēng): 544-2600
Chapter 1: Device Datasheet for Arria II Devices
1–65
Switching Characteristics
December 2013
Altera Corporation
fHSCLK_OUT (output
clock frequency)
5
717 (7)
5
717 (7)
MHz
Transmitter
fHSDR (true LVDS
output data rate)
SERDES factor, J = 3
to 10
(using dedicated
SERDES) (8)
1250
1250
Mbps
SERDES factor J = 2,
(using DDR registers)
Mbps
SERDES factor J = 1,
(uses an SDR
register)
Mbps
fHSDR (emulated
LVDS_E_3R output
data rate) (5)
SERDES factor J = 4
to 10
1152
800
Mbps
fHSDR (emulated
LVDS_E_1R output
data rate)
—200
200
Mbps
tx Jitter
Total jitter for data
rate, 600 Mbps to
1.6 Gbps
160—
—160
ps
Total jitter for data
rate, < 600 Mbps
0.1—
—0.1
UI
tx Jitter - emulated
differential I/O
standards with three
external output resistor
network
Total jitter for data
rate, 600 Mbps to
1.25 Gbps
300—
—325
ps
Total jitter for data
rate < 600 Mbps
0.2
0.25
UI
tx Jitter - emulated
differential I/O
standards with one
external output resistor
network
—0.15—
—0.15
UI
tDUTY
TX output clock duty
cycle for both True
and emulated
differential I/O
standards
45
50
55
45
50
55
%
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 2 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
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