參數(shù)資料
型號: DK-DEV-2AGX125N
廠商: Altera
文件頁數(shù): 81/90頁
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Arria? II GX FPGA Development Kit
標準包裝: 1
系列: Arria II GX
類型: FPGA
適用于相關(guān)產(chǎn)品: EP2AGX125EF35
所含物品: 板,線纜,CD,DVD,電源
產(chǎn)品目錄頁面: 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱: 544-2600
1–74
Chapter 1: Device Datasheet for Arria II Devices
Glossary
December 2013
Altera Corporation
Glossary
Table 1–68 lists the glossary for this chapter.
Table 1–68. Glossary (Part 1 of 4)
Letter
Subject
Definitions
A,
B,
C,
D
Differential I/O
Standards
Receiver Input Waveforms
Transmitter Output Waveforms
E,
F
fHSCLK
Left/Right PLL input clock frequency.
fHSDR
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
VID
p
n = 0 V
VCM
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
p
n = 0 V
VCM
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