參數(shù)資料
型號: DK-DEV-2AGX125N
廠商: Altera
文件頁數(shù): 80/90頁
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝: 1
系列: Arria II GX
類型: FPGA
適用于相關(guān)產(chǎn)品: EP2AGX125EF35
所含物品: 板,線纜,CD,DVD,電源
產(chǎn)品目錄頁面: 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱: 544-2600
Chapter 1: Device Datasheet for Arria II Devices
1–73
I/O Timing
December 2013
Altera Corporation
I/O Timing
Altera offers two ways to determine I/O timing:
Using the Microsoft Excel-based I/O Timing.
Using the Quartus II Timing Analyzer.
The Microsoft Excel-based I/O Timing provides pin timing performance for each
device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis. The
Quartus II timing analyzer provides a more accurate and precise I/O timing data
based on the specifics of the design after place-and-route is complete.
f The Microsoft Excel-based I/O Timing spreadsheet is downloadable from the
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