參數(shù)資料
型號(hào)： DK-DEV-2AGX125N
廠商： Altera
文件頁(yè)數(shù)： 76/90頁(yè)
文件大?。?/td> 0K
描述： KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊： Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Arria II GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP2AGX125EF35
所含物品： 板，線纜，CD，DVD，電源
產(chǎn)品目錄頁(yè)面： 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱： 544-2600
1–70
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Table 1–60 lists the DQS phase shift error for Arria II GX devices.
Table 1–61 lists the DQS phase shift error for Arria II GZ devices.
Table 1–62 lists the memory output clock jitter specifications for Arria II GX devices.
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria II GX
Devices (Note 1)
Number of DQS Delay Buffer
C4
I3, C5, I5
C6
Unit
1
263036
ps
2
526072
ps
3
78
90
108
ps
4
104
120
144
ps
Note to Table 1–60:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a C4 speed grade is ± 78 ps or ± 39 ps.
Table 1–61. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria II GZ
Devices (Note 1)
Number of DQS Delay Buffer
–3
–4
Unit
128
30
ps
256
60
ps
384
90
ps
4
112
120
ps
Note to Table 1–61:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a 3 speed grade is ± 84 ps or ± 42 ps.
Table 1–62. Memory Output Clock Jitter Specification for Arria II GX Devices (Note 1), (2), (3)
Parameter
Clock
Network
Symbol
–4
–5
–6
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
Global
t
JIT(per)
-100
100
-125
125
-125
125
ps
Cycle-to-cycle period
jitter
Global
t
JIT(cc)
-200
200
-250
250
-250
250
ps
Duty cycle jitter
Global
t
JIT(duty)
-100
100
-125
125
-125
125
ps
Notes to Table 1–62:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
(3) The memory output clock jitter stated in Table 1–62 is applicable when an input jitter of 30 ps is applied.
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