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參數資料
| 型號： | DK-DEV-2AGX125N |
| 廠商： | Altera |
| 文件頁數： | 60/90頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV ARRIA II GX FPGA 2AGX125 |
| 產品培訓模塊： | Arria II GX FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 特色產品： | Arria? II GX FPGA Development Kit |
| 標準包裝： | 1 |
| 系列： | Arria II GX |
| 類型： | FPGA |
| 適用于相關產品： | EP2AGX125EF35 |
| 所含物品： | 板，線纜，CD，DVD，電源 |
| 產品目錄頁面： | 605 (CN2011-ZH PDF) |
| 相關產品： | 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG 544-2598-5-ND - IC ARRIA II GX 125K 1152FBG 544-2597-5-ND - IC ARRIA II GX 125K 1152FBG |
| 其它名稱： | 544-2600 |
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Chapter 1: Device Datasheet for Arria II Devices
1–55
Switching Characteristics
December 2013
Altera Corporation
Table 1–45 lists the PLL specifications for Arria II GZ devices when operating in both
the commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
tCASC_
OUTJITTER_
PERIOD_
DEDCLK
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT
100 MHz)
—
425
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT
100 MHz)
—
42.5
mUI (p-p)
Notes to Table 1–44:
(1) fIN is limited by the I/O fMAX.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is
less than 200 ps.
(4) FREF is fIN/N when N = 1.
(5) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–62 on page 1–70.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz
Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3)
Symbol
Description
Min
Typ
Max
Unit
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency (–3 speed grade)
5
—
717 (1)
MHz
Input clock frequency (–4 speed grade)
5
—
717 (1)
MHz
fINPFD
Input frequency to the PFD
5
—
325
MHz
fVCO
PLL VCO operating range (–3 speed grade)
600
—
1,300
MHz
PLL VCO operating range (–4 speed grade)
600
—
1,300
MHz
tEINDUTY
Input clock or external feedback clock input duty cycle
40
—
60
%
fOUT
Output frequency for internal global or regional clock
(–3 speed grade)
—
700 (2)
MHz
Output frequency for internal global or regional clock
(–4 speed grade)
—
500 (2)
MHz
fOUT_EXT
Output frequency for external clock output (–3 speed grade)
—
717 (2)
MHz
Output frequency for external clock output (–4 speed grade)
—
717 (2)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
10
ns
tCONFIGPLL
Time required to reconfigure scan chain
—
3.5
—
scanclk
cycles
tCONFIGPHASE
Time required to reconfigure phase shift
—
1
—
scanclk
cycles
fSCANCLK
scanclk frequency
—
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
de-assertion of areset
——
1
ms
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