參數(shù)資料
型號： DK-DEV-2AGX125N
廠商： Altera
文件頁數(shù)： 83/90頁
文件大?。?/td> 0K
描述： KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊： Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Arria II GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP2AGX125EF35
所含物品： 板，線纜，CD，DVD，電源
產(chǎn)品目錄頁面： 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱： 544-2600
1–76
Chapter 1: Device Datasheet for Arria II Devices
Glossary
December 2013
Altera Corporation
S
SW (sampling
window)
The period of time during which the data must be valid in order to capture it correctly. The setup
and hold times determine the ideal strobe position within the sampling window:
Timing Diagram
Single-ended
Voltage
Referenced I/O
Standard
The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver
changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing:
Single-Ended Voltage Referenced I/O Standard
T
tC
High-speed receiver and transmitter input and output clock period.
TCCS
(channel-to-
channel-
skew)
The timing difference between the fastest and slowest output edges, including tCO variation and
clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under S in this table).
tDUTY
High-speed I/O block: Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL.
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL.
tRISE
Signal low-to-high transition time (20-80%).
Table 1–68. Glossary (Part 3 of 4)
Letter
Subject
Definitions
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
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