參數(shù)資料
型號: DK-DEV-2AGX125N
廠商: Altera
文件頁數(shù): 69/90頁
文件大?。?/td> 0K
描述: KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊: Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝: 1
系列: Arria II GX
類型: FPGA
適用于相關(guān)產(chǎn)品: EP2AGX125EF35
所含物品: 板,線纜,CD,DVD,電源
產(chǎn)品目錄頁面: 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱: 544-2600
Chapter 1: Device Datasheet for Arria II Devices
1–63
Switching Characteristics
December 2013
Altera Corporation
tTX_JITTER (4)
True LVDS with
dedicated
SERDES
(data rate
600–1,250
Mbps)
175
175
225
300
ps
True LVDS with
dedicated
SERDES
(data rate
< 600 Mbps)
0.105
0.105
0.135
0.18
UI
True LVDS and
emulated
LVDS_E_3R
with logic
elements as
SERDES (data
rate 600
– 945 Mbps)
260
260
300
350
ps
True LVDS and
emulated
LVDS_E_3R
with logic
elements as
SERDES
(data rate
< 600 Mbps)
0.16
0.16
0.18
0.21
UI
tTX_DCD
True LVDS and
emulated
LVDS_E_3R
45
55
45
55
45
55
45
55
%
tRISE and tFALL
True LVDS and
emulated
LVDS_E_3R
200
200
225
250
ps
TCCS
True LVDS (5)
150
150
175
200
ps
Emulated
LVDS_E_3R
200
200
250
300
ps
Receiver (6)
True differential
I/O standards -
fHSDRDPA (data
rate)
SERDES factor
J = 3 to 10
150
1250
150
1250
150
1050
150
840
Mbps
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 3 of 4)
Symbol
Conditions
I3
C4
C5,I5
C6
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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