參數(shù)資料
型號(hào)： DK-DEV-2AGX125N
廠商： Altera
文件頁(yè)數(shù)： 54/90頁(yè)
文件大?。?/td> 0K
描述： KIT DEV ARRIA II GX FPGA 2AGX125
產(chǎn)品培訓(xùn)模塊： Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Arria? II GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Arria II GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP2AGX125EF35
所含物品： 板，線纜，CD，DVD，電源
產(chǎn)品目錄頁(yè)面： 605 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG
544-2598-5-ND - IC ARRIA II GX 125K 1152FBG
544-2597-5-ND - IC ARRIA II GX 125K 1152FBG
其它名稱： 544-2600
1–50
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Sinusoidal jitter tolerance (peak-
to-peak)
Jitter Frequency = 38.2 KHz
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
> 0.5
—
UI
Jitter Frequency = 3.82 MHz
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
> 0.05
—
UI
Jitter Frequency = 20 MHz
Data rate = 6.375 Gbps
Pattern = PRBS31 BER = 10-12
> 0.05
—
UI
SDI Transmitter Jitter Generation (12)
Alignment jitter
(peak-to-peak)
Data rate = 1.485 Gbps (HD)
Pattern = color bar Low-frequency
roll-off = 100 KHz
0.2
—
0.2
—
UI
Data rate = 2.97 Gbps (3G) Pattern
= color bar Low-frequency roll-off
= 100 KHz
0.3
—
0.3
—
UI
SDI Receiver Jitter Tolerance (12)
Sinusoidal jitter tolerance (peak-
to-peak)
Jitter frequency = 15 KHz
Data rate = 2.97 Gbps (3G) Pattern
= single line scramble color bar
> 2
UI
Jitter frequency = 100 KHz
Data rate = 2.97 Gbps (3G) Pattern
= single line scramble color bar
> 0.3
UI
Jitter frequency = 148.5 MHz
Data rate = 2.97 Gbps (3G) Pattern
= single line scramble color bar
> 0.3
UI
Sinusoidal jitter tolerance (peak-
to-peak)
Jitter frequency = 20 KHz
Data rate = 1.485 Gbps (HD)
pattern = 75% color bar
> 1
UI
Jitter frequency = 100 KHz
Data rate = 1.485 Gbps (HD)
Pattern = 75% color bar
> 0.2
UI
Jitter frequency = 148.5 MHz
Data rate = 1.485 Gbps (HD)
Pattern = 75% color bar
> 0.2
UI
SAS Transmit Jitter Generation (13)
Total jitter at 1.5 Gbps (G1)
Pattern = CJPAT
—
0.55
—
0.55
UI
Deterministic jitter at 1.5 Gbps
(G1)
Pattern = CJPAT
—
0.35
—
0.35
UI
Total jitter at 3.0 Gbps (G2)
Pattern = CJPAT
—
0.55
—
0.55
UI
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 5 of 7)
Symbol/
Description
Conditions
–C3 and –I3
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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