
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Systems Inc.
14
6 Device Characteristics
(continued)
6.3 Recommended Operating Conditions
The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL and
((M + 2)/((D + 2) * f(OD))):1 with the PLL selected.
The maximum input clock (CKI pin) frequency when the PLL
is not selected as the device clock source is 50 MHz. The maximum input clock frequency is 40 MHz when
the PLL is selected.
6.3.1 Package Thermal Considerations
The maximum allowable ambient temperature, T
A
MAX
, is dependent upon the device power dissipation and is deter-
mined by the following equation:
T
A
MAX
= T
J
MAX
–
P
MAX
x
Θ
JA
Where P
MAX
is the maximum device power dissipation for the application, T
J
MAX
is the maximum device junction
temperature specified in Table 6, and
Θ
JA i
s the maximum thermal resistance in still-air-ambient specified in
Table 6. See Section 7.3 for information on determining the maximum device power dissipation.
WARNING: Due to package thermal constraints, proper precautions in the user's application should be
taken to avoid exceeding the maximum junction temperature of 120
°
C. Otherwise, the device
performance and reliability is adversely affected.
Table 5. Recommended Operating Conditions
Maximum
Internal Clock
(CLK) Frequency
200 MHz
Minimum
Internal Clock
(CLK) Period T
5.0 ns
Junction
Temperature T
J
(
°
C)
Min
–
40
Supply Voltage
V
DD
1, V
DD
1A (V)
Min
1.5
Supply Voltage
V
DD
2 (V)
Min
3.0
Max
120
Max
1.65
Max
3.6
Table 6. Package Thermal Considerations
Device Package
208 PBGA
208 PBGA
256 EBGA
256 EBGA
Parameter
Value
120
27
120
15
Unit
°
C
°
C/W
°
C
°
C/W
Maximum Junction Temperature (T
J
MAX
)
Maximum Thermal Resistance in Still-Air-Ambient (
Θ
JA
)
Maximum Junction Temperature (T
J
MAX
)
Maximum Thermal Resistance in Still-Air-Ambient (
Θ
JA
)