Data Sheet
June 2001
DSP16410B Digital Signal Processor
230
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
6 Software Architecture
(continued)
6.2 Registers
(continued)
Table 136. DMAU Memory-Mapped Registers
(continued)
6.2.2 Memory-Mapped Registers
(continued)
Table 137
summarizes the SEMI memory-mapped registers. These registers are described in detail in
Section 4.14.4 on page 108
.
Table 137. SEMI Memory-Mapped Registers
Register Name
Address
Limit
LIM0
LIM1
LIM2
LIM3
LIM4
LIM5
SBAS0
DBAS0
SBAS1
DBAS1
SBAS2
DBAS2
SBAS3
DBAS3
STR0
STR1
STR2
STR3
RI0
RI1
RI2
RI3
SWT0
SWT1
SWT2
SWT3
MMT4
MMT5
SWT0
0x42050
0x42052
0x42054
0x42056
0x42058
0x4205A
0x42040
0x42042
0x42044
0x42046
0x42048
0x4204A
0x4204C
0x4204E
0x42018
0x4201A
0x4201C
0x4201E
0x42038
0x4203A
0x4203C
0x4203E
20
R/W
data
unsigned
X
Source Base
Destination Base
Source Base
Destination Base
Source Base
Destination Base
Source Base
Destination Base
Stride
20
R/W
address
unsigned
X
SWT1
SWT2
SWT3
SWT0
SWT1
SWT2
SWT3
SWT0
SWT1
SWT2
SWT3
16
R/W
data
unsigned
X
Reindex
20
R/W
data
signed
X
Description
Size
(Bits)
16
16
16
R/W
Type
Reset Value
ECON0
ECON1
EXSEG0
EYSEG0
EXSEG1
EYSEG1
0x40000
0x40002
0x40004
0x40006
0x40008
0x4000A
SEMI Control
SEMI Status and Control
External X Segment Register for CORE0
External Y Segment Register for CORE0
External X Segment Register for CORE1
External Y Segment Register for CORE1
R/W
R/W
R/W
Control
Control
Address
0x0FFF
0
0
Some bits in this register are read-only or write-only.
With the following exceptions:
ECON1
[6,4] are a reflection of the state of external pins and are unaffected by reset, and
ECON1
[5] is set.
Type
Register
Name
Channel
Address
Size
(Bits)
R/W
Type
Signed/
Unsigned
Reset
Value
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset. Any reserved fields within the register are reset to zero.
The reindex registers are in sign-magnitude format.