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參數(shù)資料
| 型號： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動器控制器器) |
| 中文描述： | 自動CD - ROM控制器（光盤驅(qū)動器控制器器） |
| 文件頁數(shù)： | 17/102頁 |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
1-17
1.4 Pin Description
1.4.1 Pin Description in ATA Host Interface
CS1FXB
(Drive chip select 0)
This is the chip select signal decoded from the host address bus used to select the Command Block
Registers.
CS3FXB
(Drive chip select 1)
This is the chip select signal decoded from the host address bus used to select the Control Block
Registers.
DA0,1,2
(Drive address bus)
This is the chip select signal decoded from the host address bus used to select the Control Block
Registers.
DASPB
(Drive active slave present)
This is a time-multiplexed signal which indicates that a drive is active or drive 1 is present. This
signal is an open collector output with a 10K ohm pull-up resistor.
DD0-DD15
(Drive data bus)
These signals are used for 16-bit bidirection data bus between the host and the KS9245. The DD0-7
are used for accessing 8-bit ATA Task File Registers.
In ATAPI data transfer mode, it is always 16-bit wide.
DIORB
(Drive I/O Read)
This is the Read strobe signal. The rising edge of DIORB enables data from a register or the data
port of the KS9245 onto the host data bus, DD0-DD7 or DD0-DD15. The rising edge of DIORB
latches data at the host. In Ultra DMA mode, this signal is used by the Host as the DMARDYB signal
during host reads, and as the data STROBE signal during Host writes.
DIOWB
(Drive I/O Write)
This is the Write strobe signal. The rising edge of DIOWB clocks data from the host data bus, DD0-
DD7 or DD0-DD15, into the data port of the KS9245. In Ultra DMA mode, this signal is used by the
HOST as the STOP signal.
DMACKB
(DMA Acknowledge)
This signal is used by the host in response to DMARQ to either acknowledge that data has been
accepted, or that data is available.
DMARQ
(DMA Request)
This signal is used for DMA data transfer between host and KS9245. It is asserted by the KS9245
when it is ready to transfer data to or from the host. The direction of transfer is controlled by DIORB
and DIOWB. This signal is used in a handshake manner with DMACKB signal.
When a DMA operation is enabled, IOCS16B, CS1FXB and CS3FXB are not asserted and data
transfer are 16-bits wide.
IORDY
(Host IO Ready)
Pin 50
Pin 49
Pin 52,54,51
Pin 48
Pin 64,66,,68,70,73,75,77,79,
78,76,74,72,69,67,65,63
Pin 59
Pin 60
Pin 57
Pin 61
Pin 58
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相關代理商/技術參數(shù) |
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| KS9282B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS INTEGRATED CIRCUIT |
| KS9286 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR for CDP |
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