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參數(shù)資料
| 型號(hào)： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動(dòng)器控制器器) |
| 中文描述： | 自動(dòng)CD - ROM控制器（光盤驅(qū)動(dòng)器控制器器） |
| 文件頁(yè)數(shù)： | 56/102頁(yè) |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
6-6
Register 3Dh :
Acronym:
BIT 7
InValid
ECC Status Register (Read)
ECCS
BIT 5
BIT 4
EccFat
EccErr
BIT 6
OVErr
BIT 3
CBlk
BIT 2
NoSync
BIT 1
IllSync
BIT 0
Rsvd
The
ECC Status Register
is used to provide the results of ECC and EDC operations.
Bit 7: InValid (ECC Status information Invalid)
This bit is set when the succeeding ECC or DSP status has overwritten the
ECC Status Register
before firmware has read the status.
Bit 6: OVErr (DSP FIFO Overflow Error)
This bit is set when a FIFO overflow error occurs in the DSP interface.
Bit 5: EccFat (Fatal Error in ECC logic)
This bit is set when the ECC logic detected a fatal error.
Bit 4: EccErr (Uncorrectable Error block)
When this bit is set, there is an uncorrectable error in the data block.
Bit 3: CBlk (Corrected Block)
This bit is set when one or more error bytes have been corrected by the last ECC operation.
Bit 2: NoSync (No Sync Error)
This bit is set when the sync pattern was not detected in its expected location.
Bit 1: IllSync (Illegal Sync Error)
This bit is set when the sync pattern is not detected as expected.
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