參數(shù)資料
型號: KS9245
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Automated CD-ROM Controller(光盤驅(qū)動器控制器器)
中文描述: 自動CD - ROM控制器(光盤驅(qū)動器控制器器)
文件頁數(shù): 50/102頁
文件大?。?/td> 419K
代理商: KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
5-9
Bit 6: SFReset (Start Firmware Reset)
Writing a “1” to this bit causes a firmware reset for the KS9245.
Bit 5: BurstNum - Host DRAM page access burst (Byte) Size
Refer to KS9245 Performance Table below.
Bit 4: DspBurst - CD Buffer to DRAM burst size
Refer to KS9245 Performance Table below.
Bit 3: APCE (Audio Port Configuration Enable)
When this bit is set, the GP0, GP1, GP2, and GP3 pins are configured as the AWCK, ABCK,
ADAT, and DAUO pins for the audio word clock, bit clock, data, and digital audio output to an
external DAC, respectively.
Bit 2-0: Cspeed[2:0] - Adjust Arbiter’s Priority Scheme
Refer to KS9245 Performance Table below.
KS9245 Performance Table
Max Disk
Speed
Programming Value
34 X
37 X
System
Clock
Dram Type
BurstNum,DspBurst
Cspeed[2:0]
Sustain Mode
Max Host Mode
33.8 MHz
33.8 MHz
60ns Fast Page
45ns Fast Page
50ns EDO
40ns EDO
45ns Fast Page
50ns EDO
40ns EDO
45ns Fast Page
50ns EDO
[0, 0, 0, 0, 0]
[0, 0, 0, 0, 0]
PIO4 / DMA2
PIO4 / DMA2
Ultra DMA2
Ultra DMA2
50.8 MHz
50.8 MHz
50 X
45 X
[0, 0, 0, 0, 0]
[0, 0, 0, 0, 0]
Ultra DMA1
Ultra DMA1
Ultra DMA2
Ultra DMA2
50.8 MHz
50.8 MHz
35 X
32 X
[0, 1, 1, 0, 0]
[0, 1, 1, 0, 0]
Ultra DMA2
Ultra DMA2
Ultra DMA2
Ultra DMA2
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