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參數(shù)資料
| 型號(hào)： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動(dòng)器控制器器) |
| 中文描述： | 自動(dòng)CD - ROM控制器（光盤驅(qū)動(dòng)器控制器器） |
| 文件頁數(shù)： | 34/102頁 |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
2-8
Bit 4: SetHINT (Set INTRQ Signal of ATA Interface)
When this bit is set, the KS9245 asserts its INTRQ pin high.
Bit 3: ClrBSY (Clear BSY Status of ATA Task File Registers)
When this bit is set, the KS9245 clears the
BSY
bit of
ATA Status Register
.
Bit 2: ClrDASPB (Clear DASPB Signal of ATA Interface)
When this bit is set, the KS9245 drives the DASPB pin high and then releases it.
Bit 1: ClrPDIAGB (Clear PDIAGB Signal of ATA Interface)
When this bit is set, the KS9245 drives the PDIAGB pin high and then releases it.
Bit 0: ClrHINT (Clear INTRQ Signal of ATA Interface)
When this bit is set, the KS9245 negates its INTRQ pin low.
Register 0Bh:
Interface Configuration Control Register (Read)
Interface Configuration Control Register (Write)
ICC
BIT 5
BIT 4
BIT 3
ATA Transfer Mode
CDRV
SShadow
Acronym:
BIT 7
IntMode
BIT 6
BIT 2
DisShadR
BIT 1
PcmdInt
BIT 0
DisIORDY
The
Interface Configuration Control Register
is used by firmware to inform the KS9245 with specific
drive configuration such as master/slave drive and PIO/DMA etc..
Bit 7: IntMode (Interrupt Signal Mode Control)
When this bit is cleared, all interrupt events (including disk, host, and buffer) are reported via
asserting the HINTB pin. When this bit is set, interrupt events from disk/decoder are reported via
asserting DINTB pin while host/buffer interrupt events are reported via asserting the HINTB pin.
Bit 6-5: ATA Transfer Mode
These two bits specify the various ATA transfer modes.
ATA PIO/DMA Mode Selection Table
Bit 5
0
1
1
0
Bit 6
0
0
1
1
ATA data transfer mode
PIO Transfer Mode (Default)
Single Word DMA Transfer Mode
Multiword DMA Transfer Mode
Ultra DMA Transfer Mode
Bit 4: CDRV (Controller Drive Configuration)
When this bit is set, the KS9245 is configured as drive 1 (slave drive). When this bit is cleared,
the KS9245 is configured as drive 0 (master drive).
Bit 3: SShadow (Slave Shadow Feature Enabled)
This bit is used together with the
CDRV
bit. The following table summarizes the function of this bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KS9246 | ATAPI AUTOMATED CD-ROM CONTROLLER WITH EMBEDDED DRAM |
| KS9284 | Digital Signal Processor(數(shù)字信號(hào)處理器) |
| KSA1013 | PNP (COLOR TV AUDIO OUTPUT) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS9246 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:ATAPI AUTOMATED CD-ROM CONTROLLER WITH EMBEDDED DRAM |
| KS926S2 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:LOW LOSS SUPER HIGH SPEED RECTIFIER |
| KS926S2_07 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:LOW LOSS SUPER HIGH SPEED RECTIFIER |
| KS9282B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS INTEGRATED CIRCUIT |
| KS9286 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR for CDP |
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