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參數(shù)資料
| 型號： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動器控制器器) |
| 中文描述： | 自動CD - ROM控制器（光盤驅(qū)動器控制器器） |
| 文件頁數(shù)： | 9/102頁 |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
1-9
the
MP Access Physical Address LSB/MID/MSB registers
(24h, 25h, 26h)
.
This mode is used for
accessing the firmware variables such as TOC data in the System Area. Using Block Address Mode
(BAM), the block and offset addresses must be loaded into the
MP Block Address Register
(26h) and
MP
Block Offset Low/High Address Registers
(24h, 25h)
.
This mode is used to access data within the CD by
the KS9245. This allows the firmware to easily check the contents of the data block, such as Sync
Pattern, without converting the block address into a DRAM physical address. The DRAM read or write
operation will be initiated when the
SDramRd
and
SDramWrt
bits are set in the
Buffer Access Control
Register
(29h, bit 0, 1), respectively. The data for read operations will be available in the
MP Access
Data Port Register
(28h)
after the
DramBsy
bit of the
Buffer Access Control Register
is cleared (29h, bit
7). The data for write operation must be loaded into the
MP Access Data Port Register
(28h).
The write
operation will be completed when the
DramBsy
bit of the
Buffer Access Control Register
is cleared (29h,
bit 7).
Segmented Buffer support
The buffer DRAM is partitioned into two segments: The Data and System areas. The Data area, is used
for storing the CD data block as cache area while the System area is for storing CD system information
such as TOC data , Identify device information, Inquiry data, and firmware variables. The System area
starts below the last byte of the bottom of the block address which is specified in the
Buffer Bottom Block
Address Registers
(2Ch, 2Dh). Therefore, the size of the System Area can be adjustable by setting the
Buffer Bottom Block Address Registers
(2Ch, 2Dh).
Up to 64K bytes direct transfer from DRAM
Host transfers from the System Area is not limited to block boundaries. Up to 64K bytes can be directly
transferred from the buffer DRAM to the host. This allows the TOC (Table of Contents) data to be
transferred without the limitation of the 2.5K-byte or 3K-byte block boundary. This avoids having to break
a transfer into multiple sub-transfers. As a result, the firmware can support the TOC efficiently and code
size is reduced. By setting the
Transfer Offset Length Low/High 1/2 Registers
(1Eh, 1Fh, 22h, 23h) with
the desired transfer length, the transfer will not complete until the total number of bytes specified in these
registers are transferred.
1.1.4 CD Decoder Interface/Manager Functional Descriptions
The KS9245 supports various DSP devices such as Toshiba, Sony, Sanyo, and Matsushita by setting the
DSP Device Type Selection Register
(3Eh). Also, various subcode interface such as Philips V4, EIAJI
and EIAJ2 can be programmed by setting
Subcode Device Type Selection Register
(42h).
The main DSP data, C2PO error flags, and subcode buffering are supported by setting the
DSP Channel
Sel
bit in the
Buffer Configuration Control 1 Register
(2Ah, bit 6, 4, 5). Moreover, the KS9245 uses the
C2PO error flags to perform the Erasure Correction up to 2-byte error per Codeword by setting the
EraCorr
bit in the
ECC Control 1 Register
(3Bh, bit 0). The Q-subcode with de-interleaving and CRC
check are done by hardware.
Sync pattern protection logic is implemented in the KS9245 to prevent lost sync in the DSP incoming
streams. The sync patterns in buffer DRAM are further protected to facilitate the Read Raw operations.
This assures that the application is able to retrieve the correct sync pattern when Sync Insertion occurs.
The decoder logic operates in various modes according to the setting of the
Decoder Control Register
(3Ah). The Monitor Mode is used to search the target block and synchronize the Sync Mark in the main
data channel before data buffering operation occurs. In this mode, no buffering or ECC operation is
active. The decoder interrupt occurs at the relative location of Header or Subheader of the incoming
DSP data streams.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| KS9246 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:ATAPI AUTOMATED CD-ROM CONTROLLER WITH EMBEDDED DRAM |
| KS926S2 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:LOW LOSS SUPER HIGH SPEED RECTIFIER |
| KS926S2_07 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:LOW LOSS SUPER HIGH SPEED RECTIFIER |
| KS9282B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS INTEGRATED CIRCUIT |
| KS9286 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR for CDP |
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