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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
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Do Not Copy or Release
2-7
This bit is set when an error occurs during execution of the command.
Register 0Ah:
Acronym:
BIT 7
Host Interface Signal Value Register (Read)
HISV
BIT 6
BIT 5
BIT 4
Reserved
BIT 3
MSTB
BIT 2
DASPB
BIT 1
PDIAGB
BIT 0
0
The
Host Interface Signal Value Register
monitors the ATA interface signals. The microprocessor
can read this register to check the state of the MSTB/DASPB/PDIAGB signals. For example, the
PDIAGB and DASPB signals are required by firmware to process master/slave handshaking.
Bit 7-4: Reserved
These bits are reserved for future enhancements.
Bit 3: MSTB (MSTB Master/Slave Pin Signal)
This bit reflects the state of the
MSTB
pin. This bit is “1” when the
MSTB
pin is high. This bit is
“0” when the
MSTB
pin is low.
Bit 2: DASPB (DASPB Signal of ATA Interface)
This bit reflects the physical state of the
DASPB
pin. When this bit is “1”, the
DASPB
pin is high
(not asserted). When this bit is “0”, the
DASPB
pin is low (asserted).
Bit 1: PDIAGB (PDIAGB Signal of ATA Interface)
This bit reflects the physical state of the
PDIAGB
pin. When this bit is “1”, the
PDIAGB
pin is high
(not asserted). When this bit is “0”, the
PDIAGB
pin is low (asserted).
Bit 0: Reserved
This bit is reserved for future enhancements.
Register 0Ah:
Acronym:
BIT 7
SetBSY
Host Interface Control Register (Write)
HIC
BIT 5
BIT 4
SetDASPB
SetPDIAGB
SetHINT
BIT 6
BIT 3
ClrBSY
BIT 2
ClrDASPB
BIT 1
ClrPDIAGB
BIT 0
ClrHINT
The
Host Interface Control Register
controls the
BSY
status of the ATA Status Register and the
PDIAGB
,
DASPB
and
INTRQ
pins of ATA interface signals.
Bit 7: SetBSY (Set BSY Status of ATA Task File Registers)
When this bit is set, the KS9245 sets the
BSY
bit of
ATA Status Register
.
Bit 6: SetDASPB (Set DASPB Signal of ATA Interface)
When this bit is set, the KS9245 asserts its DASPB pin low.
Bit 5: SetPDIAGB (Set PDIAGB Signal of ATA Interface)
When this bit is set, the KS9245 asserts its PDIAGB pin low.