參數(shù)資料
型號: KS9245
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Automated CD-ROM Controller(光盤驅(qū)動器控制器器)
中文描述: 自動CD - ROM控制器(光盤驅(qū)動器控制器器)
文件頁數(shù): 47/102頁
文件大?。?/td> 419K
代理商: KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
5-6
Register 28h :
MP Access Data Port Register (Read)
MP Access Data Port Register (Write)
MPDP
BIT 5
BIT 4
MP Access Data Port B7:B0
Acronym:
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
The
MP Access Data Port Register
is used to access the content of the DRAM for both read and
write operations.
Register 29h :
Acronym:
BIT 7
DramBsy
Buffer Access Control Register (Read)
BAC
BIT 5
BIT 4
BIT 3
Reserved
BIT 6
BIT 2
PAMb
BIT 1
Rsvd
BIT 0
Rsvd
Bit 7: DramBsy (DRAM Busy Status)
This bit set when the DRAM is busy.
Bit 6-3: Reserved
These bits are reserved for future enhancements.
Bit 2: PAMb (Physical Addressing Mode Disabled)
When this bit is reset, Physical Addressing Mode (PAM) is used for DRAM accesses by the
microprocessor. When this bit is set, Block Addressing Mode (BAM) is used for DRAM accesses
by the microprocessor. Also, refer to the
MP Access Physical Address LSB Register
(24h)
description.
Bit 1-0: Reserved
These bits are reserved for future enhancements.
Register 29h :
Acronym:
BIT 7
IncAudCnt
Buffer Access Control Register (Write)
BAC
BIT 5
BIT 4
Reserved
BIT 6
IncBlkCn
t
BIT 3
BIT 2
PAMb
BIT 1
SDramWrt
BIT 0
SDramRd
Bit 7: IncAudCnt
Writing a “1” to this bit increments the
Valid Audio Block Count Register
(48h) by one. Writing a
“0” to this bit causes no operation.
Bit 6: IncBlkCnt
Writing a “1” to this bit increments the
Valid Cache Block Count Register
(14h) by one
.
Bit 5-3: Reserved
These bits are reserved for future enhancements.
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