參數(shù)資料
型號(hào)： KS9245
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Automated CD-ROM Controller(光盤驅(qū)動(dòng)器控制器器)
中文描述： 自動(dòng)CD - ROM控制器（光盤驅(qū)動(dòng)器控制器器）
文件頁(yè)數(shù)： 63/102頁(yè)
文件大?。?/td> 419K
代理商： KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
6-13
Register 4Dh :
DAC Control Register (Read)
DAC Control Register(Write)
DACR
BIT 6
BIT 5
Reserved
Acronym:
BIT 7
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SPA
ACC
The
DAC Control Register
controls various DAC output operations such as mono, stereo, and swap
left / right channel modes.
Bit 7-3: Reserved
These bits are reserved for future enhancements.
Bit 2-1: ACC (Audio Channel Control)
These bits control various audio channel outputs.
Bit 0: SPA (Start Play Audio)
When this bit is set and the ABPS bit is 0, the KS9245 starts outputting the audio data pointed to
by the
DAC Block Address Register
(4Ah).
Register 4Eh :
Audio Clock Control Register (Read)
Audio Clock Control Register(Write)
ACCR
BIT 6
BIT 5
BIT 4
ABPS
DAUE
Acronym:
BIT 7
Rsvd
BIT 3
BIT 2
DSCD
BIT 1
BIT 0
DOVS
XINA Div
The
Audio Clock Control Register
selects the audio clock source and various audio enables for
Bypass mode and Digital Audio as well as the DSP input oversampling rate.
Bit 7 Reserved
This bit is reserved for future enhancements.
Bit 6: ABPS (Audio Bypass Mode Start)
When this bit is set regardless of what mode the CD decoder is in, the audio data is directly
selected from the DSP input and then output to AWCK / ABCK / ADAT / DAUO pins. When this bit
is cleared, the audio Bypass Mode is disabled.
Bit 5: DAUE (Digital Audio Output Enable)
Writing an “1” to this bit enables the Digital Audio output, IEC 958, on Pin 4.
Bit 4-3: DOVS (DSP Input Over Sampling Rate)
These bits select the over-sampling rate for the DSP input
.
Bit 2: DSCD (Disable Subcode Clock Detect)
When this bit is set, the subcode clock auto-detection is disabled and the Subcode Clock Control
and Adjustments Registers (40h, 45h, and 46h) are valid. When this bit is cleared, the subcode
clock auto-detection is enabled and the Subcode Clock Control Register is invalid.
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