參數(shù)資料
型號(hào)： KS9245
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Automated CD-ROM Controller(光盤驅(qū)動(dòng)器控制器器)
中文描述： 自動(dòng)CD - ROM控制器（光盤驅(qū)動(dòng)器控制器器）
文件頁(yè)數(shù)： 18/102頁(yè)
文件大?。?/td> 419K
代理商： KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
1-18
This signal is deasserted in order to extend the host access when KS9245 is not ready to response to
the request. In Ultra DMA mode, this signal is used by the KS9245 as the drive’ s DMARDYB signal
during Host writes, and as the drive’ s data STROBE signal during Host reads.
INTRQ
(Drive interrupt)
This signal is used to interrupt the host. INTRQ pin is asserted only when the KS9245 has a pending
interrupt while the drive is selected, and the host has cleared nIEN in the ATA Device Control
Register. If nIEN=1 or the drive is not selected, this output is in a high impedance state, regardless of
the presence or absence of a pending interrupt.
Pin 56
IOCS16B
(Device 16-bit I/O)
Except for DMA transfers, IOC16B indicates to the host that the 16-bit data port has been addressed.
This is an open collector output.
Pin 55
In ATAPI PIO data transfer mode, the IOCS16B shall always be asserted.
PDIAGB
(Drive passed diagnostics)
This signal is asserted by drive 1 (slave drive) to indicate to drive 0 (master drive) that it has
completed diagnostics. A 10K ohm pull-up resistor is used on this signal by each drive on the same
cable.
Pin 53
HRSTB
(ATA Host Reset)
This signal from the host system is asserted for at least 25 usec after voltage levels during power-on
and negated thereafter unless some event requires that the drive be reset following power on. When
this input signal is asserted, the ATA Task File Registers will be initialized and the BSY bit in ATA
Status Register will be set. The
Hrst
bit in
Host Interrupt Status Register
will be set (10h, bit 3) , if
HrstE
bit in
Host Interrupt Mask Register
(12h, bit 3) is set.
Pin 80
1.4.2 Pin Description in Buffer DRAM Interface
BDAT 0-15
(Buffer DRAM data bus)
Pin 12,9,7,5,3,1,99,97,95,98,100,2,4,6,
8,11
These signals are used for buffer DRAM data bus with 16-bit parallel data path to/from the buffer
memory.
BADD 0-8
(Buffer DRAM address bus)
These signals are used for buffer DRAM address bus. Up to 512K bytes DRAM are supported by
KS9245.
Pin 89,87,84,82,81,83,86,88,91
IMPORTANT: BADD5 pin 83 must also be pulled high by a 22K Ohm resistor.
CASB
(Column address strobe)
This signal is used as column address strobe for buffer DRAM.
Pin 93
RASB
(Row address strobe)
This signal is used as row address strobe for buffer DRAM.
Pin 92
WEB
(DRAM write enable)
This signal is used as the memory write enable for buffer DRAM.
Pin 94
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