參數(shù)資料
型號(hào)： KS9245
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Automated CD-ROM Controller(光盤(pán)驅(qū)動(dòng)器控制器器)
中文描述： 自動(dòng)CD - ROM控制器（光盤(pán)驅(qū)動(dòng)器控制器器）
文件頁(yè)數(shù)： 37/102頁(yè)
文件大?。?/td> 419K
代理商： KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
3-2
Register 0Fh :
Acronym:
BIT 7
ACacheE
Transfer Sequence Command Register (Write)
TSC
BIT 5
BIT 4
BIT 3
Rsvd
SSxfr
Sabort
BIT 6
ACplE
BIT 2
SPause
BIT 1
WRDir
BIT 0
SDxfr
The
Transfer Sequence Command Register
is used to start or control the ATAPI host transfer
operations.
Bit 7: ACacheE (Automated Cache Control)
When the
ACacheE
bit is “1”, the Auto Cache Mode is enabled and host transfers are completely
automated
.
When the
ACacheE
bit is “0”, the Auto Cache Feature is disabled
.
Bit 6: ACplE (Automated Command Completion Enabled)
When this bit is set, the ATAPI command completion sequence will automatically start when any of
the following events occur:
The
Total Host Transfer Length Register
is decreased to zero when the host transfer is in the
Data Area and initialized by setting the
SDxfr
bit in the
Transfer Sequence Command Register
(0Fh, bit 0).
The host transfer is in the System Area and initialized by setting the
SSxfr
bit in
Transfer
Sequence Command Register
(0Fh, bit 4).
Bit 5: Reserved
This bit is reserved for future enhancements.
Bit 4: SSxfr (Start Host Transfer Operation in System Area)
When this bit is “1”, the KS9245 starts host transfer operations to / from the System Area.
Bit 3: SAbort (Start Transfer Abort Operation)
This function is used to abort the host transfer in an emergent occasion such as an abort command
or eject disc occurrence. When this bit is set, the KS9245 aborts the current host transfer
operation immediately.
Bit 2: SPause (Start Host Transfer Pause Operation)
When this bit is set, the KS9245 pauses the host transfer operation when the transfer in the
Current Host Transfer Length Register
(18h) are complete.
Bit 1: WRDir (Write/Read Direction Control)
When this bit is set, the host is transferring data to KS9245. When this bit is reset, the host is
reading data from the KS9245
.
Bit 0: SDxfr (Start Host Transfer Operation in Data Area)
When this bit is set, the KS9245 starts host block transfer operations.
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