參數(shù)資料
型號(hào)： KS9245
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Automated CD-ROM Controller(光盤(pán)驅(qū)動(dòng)器控制器器)
中文描述： 自動(dòng)CD - ROM控制器（光盤(pán)驅(qū)動(dòng)器控制器器）
文件頁(yè)數(shù)： 41/102頁(yè)
文件大?。?/td> 419K
代理商： KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
4-3
Bit 3: HrstE(ATA Host Rest Interrupt Enabled)
When this bit is set, the
Hrst
interrupt (10h, bit 3) is enabled. When this bit is reset, the
Hrst
interrupt is disabled.
Bit 2: ScmdRcvE (Shadow Command Interrupt Enabled)
When this bit is set, the
ScmdRcv
interrupt (10h, bit 2) is enabled. When this bit is reset, the
ScmdRcv
interrupt is disabled.
Bit 1: AcmdRcvE (ATA Command Interrupt Enabled)
When this
bit is set, the
AcmdRcv
(10h, bit 1) interrupt is enabled. When this bit is reset, the
AcmdRcv
interrupt is disabled.
Bit 0: PcmdRcvE (ATAPI Packet Command Interrupt Enabled)
When this bit is set, the
PcmdRcv
interrupt (10h, bit 0) is enabled. When this bit is reset, the
PcmdRcv
interrupt is disabled.
Register 13h:
Decoder Interrupt Mask Register (Read)
Decoder Interrupt Mask Register (Write)
DIM
BIT 5
BIT 4
BIT 3
Reserved
Acronym:
BIT 7
BIT 6
BIT 2
DACIntE
BIT 1
SubIntE
BIT 0
DecIntE
This register controls the masking for each interrupt source. Writing a “1” to each bit enables the
interrupt for that corresponding function. Writing a “0” to each bit, disables the interrupt for that
corresponding function.
Bit 7-3: Reserved
These bits are reserved for future enhancements.
Bit 2: DACIntE (Audio DAC Output Interrupt Enable)
When this bit is set, the
DACInt
interrupt (11h, bit 2) is enabled. When this bit is reset, the
DACInt
interrupt is disabled.
Bit 1: SubIntE (CD Subcode Interrupt Enabled)
When this bit is set, the
SubInt
interrupt (11h, bit 1) is enabled. When this bit is reset, the
SubIntE
interrupt is disabled.
Bit 0: DecInt (CD Decoder Interrupt)
When this bit is set, the
DecInt
interrupt (11h, bit 0) is enabled. When this bit is reset, the
DecInt
interrupt is disabled.
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