參數(shù)資料
型號(hào)： KS9245
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Automated CD-ROM Controller(光盤驅(qū)動(dòng)器控制器器)
中文描述： 自動(dòng)CD - ROM控制器（光盤驅(qū)動(dòng)器控制器器）
文件頁(yè)數(shù)： 48/102頁(yè)
文件大?。?/td> 419K
代理商： KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
5-7
Bit 2: PAMb (Physical Addressing Mode Disabled)
Writing a “0” to this bit places the KS9245 into Physical Addressing Mode (PAM) for DRAM
accesses. Writing a “1” to this bit places the KS9245 into Block Addressing Mode (BAM) for DRAM
accesses
.
Bit 1: SDramWrt (Start DRAM Write)
Writing a “1” to this bit causes the KS9245 to start the DRAM write operation.
Bit 0: SDramRd (Start DRAM Read)
Writing a “1” to this bit causes the hardware to start the DRAM read operation.
Register 2Ah :
Buffer Configuration Control 1 Register (Read)
Buffer Configuration Control 1 Register (Write)
BCC1
BIT 5
BIT 4
BIT 3
Ssel
Csel
BlkConf
DSP Channel Sel
BlkConf
Acronym:
BIT 7
C2ErrOR
C2ErrOR
BIT 6
Dsel
BIT 2
BIT 1
Dramsz
Dramsz
BIT 0
The
Buffer Configuration Control 1 Register
specifies the DRAM size and configuration.
Bit 7: C2ErrOR(C2 Error Block OR Format)
When this bit is set, the first byte of C2 Block Error is the result of logically ORing all of the C2
Error Flag bytes. When this bit is cleared, the first byte of the C2 Block Error is the longitudinal
parity (XOR) of all the C2 Error Flag bytes.
Bit 6-4 : DSP Channel Sel (DSP Channel Select for Buffering)
The
DSP Channel Sel
bits select various DSP data channels to be buffered when the decoder is in
Buffer Only / ECC / Audio Buffering / Test Modes.
Bit 6: Dsel (Data Channel Select DSP for Buffering)
Writing a “1” to this bit selects the DSP main data channel for buffering. Writing a “0” to this bit
disables the DSP main data channel and prevents it from being buffered.
Bit 5: Ssel (Subcode Channel Select DSP for Buffering)
Writing a “1” to this bit selects the DSP subcode channel for buffering. Writing a zero to this bit
disables the DSP subcode channel and prevents it from being buffered.
Bit 4: Csel (C2P0 Channel Select DSP for Buffering)
Writing a “1” to this bit, selects the DSP C2PO error flags for buffering. Writing a “0” to this bit
prevents the DSP C2PO error flags from being buffered.
Bit 3: BlkConf (DRAM Block Configuration)
This bit configures the CD Block size in DRAM. When this bit is set, each CD Block size is
partitioned as 2.5K (2560 bytes). When this bit is cleared, each CD Block size is partitioned as 3K
(3072 bytes).
Bit 2-0: Dramsz (DRAM Size Selection)
These bits specify the DRAM size.
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