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參數(shù)資料
| 型號： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動器控制器器) |
| 中文描述： | 自動CD - ROM控制器（光盤驅(qū)動器控制器器） |
| 文件頁數(shù)： | 5/102頁 |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
1-5
1.1. Functional and Features Description
1.1.1
Microprocessor Interface Functional Descriptions
Intel and Motorola microprocessor interface support
The KS9245 supports both Intel and Motorola type microprocessor interfaces with multiplexed
addressing mode. In this mode, the microprocessor address and data lines are shared in AD0-7 pins.
Addresses are latched on the trailing edge of the ALE signal. The RDB/WRB pins are used as read and
write strobes respectively. Supporting both Intel and Motorola type microprocessors directly enhances
the flexibility of the KS9245.
Combined host/buffer and disk interrupt circuit
The KS9245 supports host/buffer interrupts via the HINTB pin and decoder/disk interrupts via the DINTB
pin. Using separate interrupt signals, the interrupt priorities are easily realized. This increases the real-
time firmware processing capabilities for high speed CD-ROM applications.
Also, all interrupts can be combined onto the HINTB pin by clearing the
IntMode
bit in the
Interface
Configuration Control Register
(0Bh, bit 7). When power-on or reset occurs, the combined interrupt on
the HINTB pin is the default configuration.
The host/buffer interrupt includes host command received, reset, or data transfer completed interrupts.
The decoder interrupt includes CD decoder or subcode interrupts. The interrupt status is reported in the
Host Interrupt Status Register
(10h) and the
Decoder Interrupt Status Register
(11h).
Both HINTB and DINTB are active low, level triggered signals. With the organized interrupt control in the
Host Interrupt Clear/Mask Register
(10h) and
Disk Interrupt Clear/Mask Register
(11h), the firmware is
ensured of obtaining interrupts without accidentally clearing or disabling of the interrupts. As a result,
reliability of real-time process is achieved.
Polling mode for interrupt processing is also supported in the KS9245 by clearing the mask bits in
Host
Interrupt Mask Register
(10h) and
Disk Interrupt Mask Register
(11h).
Direct register access from microprocessor
The KS9245 supports direct register accesses. Normally, no external glue logic is required to use this
feature. Using direct register access, firmware overhead is minimized and system performance
enhanced.
General purpose IO pins support
Four General purpose I/O pins are supported in the KS9245. They are the GPIO0-3 pins. Also, these
pins are shared with Audio Output pins AWCK/ABCK/ADAT. When the APCE bit in the
Global
Configuration Register
(2F, Bit 3) is set, these pins are configured as general purpose Input or Output
functions. These pins can be configured as Input or Output by programming the
Port Control Register
(44h, Bit 7, Bit 6, Bit 5, Bit4). These pins may be used for Eject, CD tray, and volume, etc. controls
without external glue logic.
Power Management/Auto wake-up support
The Sleep Mode power management is supported by KS9245. In this mode, the Decoder, Buffer
Manager, and host interface circuits are in power savings mode. During Sleep Mode, the buffer DRAM
contents are sustained by the KS9245’ s internal refresh logic and the ATA Task File Registers are
available to the host. The Sleep Mode is enabled by setting
SSleep
bit in
Global Control Register
(2Fh,
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