參數(shù)資料
型號(hào)： LXT970A
廠商： Intel Corp.
英文描述： Dual-Speed Fast Ethernet Transceiver
中文描述： 雙速度快速以太網(wǎng)收發(fā)器
文件頁(yè)數(shù)： 11/74頁(yè)
文件大小： 1061K
代理商： LXT970A
Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Datasheet
11
Table 2. LXT970A MII Signal Descriptions
Pin#
1
Pin Name
I/O
2,3
Signal Description
4
MII Data Interface Pins
63
62
61
60
59
TXD4
TXD3
TXD2
TXD1
TXD0
I
Transmit Data
. The Media Access Controller (MAC) drives data to the
LXT970A using these inputs. TXD4 is monitored only in Symbol (5B) Mode.
These signals must be synchronized to the TX_CLK.
58
TX_EN
I
Transmit Enable
. The MAC asserts this signal when it drives valid data on the
TXD inputs. This signal must be synchronized to the TX_CLK.
57
TX_CLK
I/O
Transmit Clock
. Normally the LXT970A drives TX_CLK; in Slave Clock Mode,
TX_CLK is an input. Refer to the Clock Requirements discussion in the
Functional Description section on
page 18
.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
56
TX_ER
I
Transmit Coding Error
. The MAC asserts this input when an error has
occurred in the transmit data stream. When the LXT970A is operating at 100
Mbps, the LXT970A responds by sending invalid code symbols on the line.
46
47
48
49
50
RXD4
RXD3
RXD2
RXD1
RXD0
O
Receive Data
. The LXT970A drives received data on these outputs,
synchronous to RX_CLK.
RXD4 is driven only in Symbol (5B) Mode.
51
RX_DV
O
Receive Data Valid
. The LXT970A asserts this signal when it drives valid data
on RXD. This output is synchronous to RX_CLK.
55
RX_ER
O
Receive Error
. The LXT970A asserts this output when it receives invalid
symbols from the network. This signal is synchronous to RX_CLK.
54
RX_CLK
O
Receive Clock
. This continuous clock provides reference for RXD, RX_DV, and
RX_ER signals. Refer to the Clock Requirements discussion in the Functional
Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
64
COL
O
Collision Detected
. The LXT970A asserts this output when detecting a
collision. This output remains High for the duration of the collision.
This signal is asynchronous and inactive during full-duplex operation.
1
CRS
O
Carrier Sense
. During half-duplex operation (bit 0.8 = 0), the LXT970A asserts
this output when either transmit or receive medium is non-idle. During full-
duplex operation (bit 0.8 = 1) or repeater operation
(bit 19.13 = 1), CRS is asserted only when the receive medium is non-idle.
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. If bit 17.3 = 0, 55
series termination resistors are recommended on all output signals to avoid undershoot/overshoot, even
on short traces.
If bit 17.3 = 1, termination resistors are not required.
4. The LXT970A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an
“
X.Y
”
notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
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