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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 14/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
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LXT970A
—
Dual-Speed Fast Ethernet Transceiver
14
Datasheet
Table 7. LXT970A Hardware Control Interface Signal Descriptions
Pin#
1
Pin Name
I/O
2
Signal Description
3
8
7
6
5
4
MF0
MF1
MF2
MF3
MF4
I
Multi-Function (MF)
. Five dual-function configuration inputs. Each pin accepts one of four
input voltage levels (V
MF
1 = 5V, V
MF
2 = 3.5V, V
MF
3 = 1.5V, V
MF
4 = 0V).
A simple resistor divider network, as shown in
Figure 20 on page 45
, is required to establish
Mid-level (V
MF
2 and V
MF
3) settings. V
MF
1 and V
MF
4 (default) settings, can be established
with the LXT970A standard power supply and do not require a voltage divider. One voltage
divider may be used to drive the MF pins in designs using multiple LXT970A
’
s.
Each MF pin internally drives two different configuration functions. The first function
determines the 5-bit address that the LXT970A responds to on the MDIO line. The second
function determines a particular operational mode of the LXT970A. Each MF pin also
determines the state of a particular bit in the MII registers. The MDDIS input determines if this
effect occurs only at initialization (MDDIS = 0) or continuously (MDDIS = 1). The relationship
between the input levels and the two configuration functions are shown in
Table 8 on page 16
and
Table 9 on page 17
.
The operating functions of MF4, CFGO, and CFG1 change depending on the state of MF0
(Auto-Negotiation enabled or disabled). The functions of MF4, CFG1 and FDE are
interrelated.
The functions of the five MF inputs are as follows:
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. FDE, CFG0, and CFG1 are affected by the MDDIS input pin. When MDDIS = 0, these inputs determine only the initial state
of the function they control. When MDDIS = 1, these inputs provide continuous hardware control over their corresponding
functions.
Pin
MII Address
MII Bit
Operating Function
MF0
0
0.12
Auto-Negotiation
MF1
1
19.13
Repeater Mode (Disabling DTE Mode)
MF2
2
19.4
5B Symbol Mode (Disabling 4B Nibble Mode)
MF3
3
19.3
Scrambler Operation (Disabling Scrambler)
MF4
4
4.7
4.8
Auto-Negotiation Enabled - Advertise 100 Mbps
19.2
Auto-Negotiation Disabled - Selects TX/FX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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