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參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 43/74頁 |
| 文件大小： | 1061K |
| 代理商： | LXT970A |
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Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Datasheet
43
The recommended implementation is to divide the VCC plane into two sections. The digital
section supplies power to the digital VCC pin, VCCIO pin, and to the external components. The
analog section supplies power to VCCA, VCCT, and VCCR pins of the LXT970A. The break
between the two planes should run under the device. In designs with more than one LXT970A, a
single continuous analog VCC plane can be used to supply them all.
The digital and analog VCC planes should be joined at one or more points by ferrite beads. The
beads should produce at least a 100
impedance at 100 MHz. The beads should be placed so that
current flow is evenly distributed. The maximum current rating of the beads should be at least
150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10
μ
F) should
be placed on each side of each ferrite bead to stop switching noise from traveling through the
ferrite.
In addition, a high-frequency bypass cap (.01
μ
f) should be placed near each analog VCC pin.
3.3.3
Ground Noise
The best approach to minimize ground noise is strict use of good general design guidelines and by
filtering the VCC plane.
3.3.4
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes. The following
guidelines are recommended:
Follow the guidelines in the
LXT970 Layout Guide
for locating the split between the digital
and analog VCC planes.
Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, away from the
magnetics, and away from the RJ-45 connectors.
The ground plane should be one continuous, unbroken plane.
Place the layers so that the TPOP/N and TPIP/N signals can be routed near or next to the
ground plane. It is more important to shield TPOP/N than TPIP/N for EMI reasons.
3.3.5
Interfaces for Twisted-Pair /Fiber
3.3.5.1
Twisted-Pair
Figure 21 on page 46
shows the recommended termination circuits for the fiber and twisted-pair
interfaces. The twisted-pair interface consists of magnetics and a 100
termination resistance in
parallel on the device-side of the winding. On the transmit pair, a common-mode bypass capacitor
to ground is strongly recommended. A similar technique on the receive side can improve
performance in some cases, however the results are highly application specific and must be
verified. Route TREF nearby, but not in-between TPOP and TPON. A
“
Bob Smith
”
termination is
often provided for the unused signal pairs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
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