參數(shù)資料
型號(hào)： LXT970A
廠(chǎng)商： Intel Corp.
英文描述： Dual-Speed Fast Ethernet Transceiver
中文描述： 雙速度快速以太網(wǎng)收發(fā)器
文件頁(yè)數(shù)： 44/74頁(yè)
文件大?。?/td> 1061K
代理商： LXT970A
LXT970A
—
Dual-Speed Fast Ethernet Transceiver
44
Datasheet
3.3.5.2
Fiber
The fiber interface consists of a pseudo-ECL transmit and receive pair to an external fiber optic
transceiver. The transmit pair should be AC-coupled to the transceiver, and biased to 3.7V with a
50
equivalent impedance. The receive pair can be DC-coupled, and should be biased to 3.0V with
a 50
equivalent impedance.
Figure 21 on page 46
shows the correct bias networks to achieve
these requirements.
The following guidelines apply to when laying out any differential pair:
Space both members close together allowing nothing to come between them.
Keep distances as short as possible, both traces should have the same length.
Avoid layer changes as much as possible.
Keep termination circuits close together and on the same side of the board.
Always put termination circuits close to the source end of any circuit.
3.3.6
Interface for the MII
3.3.6.1
Transmit Hold Time Adjustment
Transmit hold time for TXD, TX_EN, and TX_ER from TX_CLK High is currently specified in
Table 32
,
Table 34
,
Table 36
, and
Table 38
as 5 ns minimum. 0 ns minimum is the IEEE
specification. Depending on the specification of the MAC or ASIC used in your design, you may or
may not need to account for this in your PC board design.
If you determine that a timing adjustment is required, there are a couple of recommended ways to
do this.
If using series resistors in the TXD lines, increase the value of the resistors to achieve the
necessary delay.
An alternative method is to add the appropriate delay in the TX_CLK line. Depending on the
amount of delay required, this may be accomplished with a series resistor or by adding a buffer
to the TX_CLK line.
Note that some delay is introduced by the actual PC board traces themselves.
3.3.6.2
MII Terminations
When the LXT970A is configured with high-strength MII driver levels (bit 17.3 = 0), 55
series
termination resistors are recommended on all MII output signals to avoid undershoot and
overshoot.
When 17.3 = 1, the MI driver levels are reduced by a factor of ten and termination resistors are not
required on the MII outputs.
相關(guān)PDF資料
PDF描述
LXT970 Fast Ethernet Transceiver
LXT970QC Fast Ethernet Transceiver
LXT971A 3.3V Dual-Speed Fast Ethernet PHY Transceiver
LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972ALC 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT970AQC 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述:
LXT970AQC.B11 制造商:Intel 功能描述:
LXT970ATC 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Telecomm/Datacomm
LXT970QC 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP
LXT971A 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*