- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377799 > LXT970A (Intel Corp.) Dual-Speed Fast Ethernet Transceiver PDF資料下載
參數(shù)資料
| 型號： | LXT970A |
| 廠商： | Intel Corp. |
| 英文描述： | Dual-Speed Fast Ethernet Transceiver |
| 中文描述： | 雙速度快速以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 25/74頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | LXT970A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
Dual-Speed Fast Ethernet Transceiver
—
LXT970A
Datasheet
25
and an optional interrupt line (MDINT). The LXT970A can signal an interrupt using the MDIO
signal as shown in
Figure 8
. The user can also assign a separate pin for this function. If bit 17.1 = 1,
pin 2 (FDS/MDINT) will be used as an MDINT pin.
The protocol allows one controller to communicate with multiple LXT970A devices. The MF pins
control one bit each of the 5-bit address setting. Each LXT970A is assigned an MII address
between 0 and 31. Details of the MF inputs are shown in
Table 7 on page 14
. Timing for the MDIO
Interface is shown in
Table 42 on page 61
. Read and write operations are shown in
Figure 9
and
Figure 10
. Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High,
the MDIO operates as a read-only interface. When MDDIS is Low, read and write are enabled.
The LXT970A supports twelve 16-bit MDIO registers. Registers 0-6 are required and their
functions are specified by the IEEE 802.3 specification. Additional registers are included for
expanded functionality. The MDIO Register set for the LXT970A is described in
Table 45
through
Table 56
. Specific bits in the registers are referenced using an
“
X.Y
”
notation, where X is the
register number (0-6 or 16-20) and Y is the bit number (0-15).
MII Management Interrupt
The MDINT/FDS pin functions as a management data interrupt on the MII when 17.1 = 1. An
active Low on this pin indicates a status change on the LXT970A. The interrupt is activated when
changes are made to the following conditions:
Link Status
Duplex Status
This interrupt is cleared by sequentially reading Register 1 and Register 18.
Figure 8. MDIO Interrupt Signaling
Figure 9. Management Interface - Read Frame Structure
Figure 10. Management Interface - Write Frame Structure
MDC
MDIO
Interrupt
Turn
Around
Z
Idle
0
INT
Read Data
Sourced by
LXT970A
MDIO FRAME
MDC
MDIO
(Read)
32 "1"s
0
1
1
0
Preamble
SFD
Op Code
PHY Address
Turn
Z
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
Data
Idle
Write
Read
D15
D14
D1
D0
Idle
MDC
MDIO
(Write)
32 "1"s
0
1
0
1
Preamble
SFD
Op Code
PHY Address
Turn
Around
1
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
D0
Data
Idle
Idle
Write
相關PDF資料 |
PDF描述 |
|---|---|
| LXT970 | Fast Ethernet Transceiver |
| LXT970QC | Fast Ethernet Transceiver |
| LXT971A | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC | 制造商:LEVEL ONE 功能描述: 制造商:LEVELONE 功能描述: 制造商: 功能描述: 制造商:LEVEL1 功能描述: |
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。